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preliminary user? manual printed in japan document no. u12022ej4v0um00 (4th edition) date published january 1998 n cp(k) 1996 m pd780021 m pd780031 m pd780021y m pd780031y m pd780022 m pd780032 m pd780022y m pd780032y m pd780023 m pd780033 m pd780023y m pd780033y m pd780024 m pd780034 m pd780024y m pd780034y m pd780021(a) m pd780031(a) m pd780021y(a) m pd780031y(a) m pd780022(a) m pd780032(a) m pd780022y(a) m pd780032y(a) m pd780023(a) m pd780033(a) m pd780023y(a) m pd780033y(a) m pd780024(a) m pd780034(a) m pd780024y(a) m pd780034y(a) m pd78f0034 m pd78f0034y m pd780024, 780034, 780024y, 780034y subseries 8-bit single-chip microcontrollers
2 [memo]
3 fip, eeprom, and iebus are trademarks of nec corporation. windows, and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. ethernet is a trademark of xerox corp. news and news-os are trademarks of sony corporation. osf/motif is a trademark of opensoftware foundation, inc. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
4 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: m pd78f0034cw, 78f0034gc-ab8, 78f0034gk-8a8 m pd78f0034ycw, 78f0034ygc-ab8, 78f0034ygk-8a8 the customer must judge the need for a license for the following products: m pd780021cw-xxx, 780022cw-xxx, 780023cw-xxx, 780024cw-xxx m pd780021gc-xxx-ab8, 780022gc-xxx-ab8, 780023gc-xxx-ab8 m pd780024gc-xxx-ab8, 780021gk-xxx-8a8, 780022gk-xxx-8a8 m pd780023gk-xxx-8a8, 780024gk-xxx-8a8, 780021cw(a)-xxx m pd780022cw(a)-xxx, 780023cw(a)-xxx, 780024cw(a)-xxx m pd780021gc(a)-xxx-ab8, 780022gc(a)-xxx-ab8, 780023gc(a)-xxx-ab8 m pd780024gc(a)-xxx-ab8, 780021gk(a)-xxx-8a8, 780022gk(a)-xxx-8a8 m pd780023gk(a)-xxx-8a8, 780024gk(a)-xxx-8a8, 780021ycw-xxx m pd780022ycw-xxx, 780023ycw-xxx, 780024ycw-xxx m pd780021ygc-xxx-ab8, 780022ygc-xxx-ab8, 780023ygc-xxx-ab8 m pd780024ygc-xxx-ab8, 780021ygk-xxx-8a8, 780022ygk-xxx-8a8 m pd780023ygk-xxx-8a8, 780024ygk-xxx-8a8, 780021ycw(a)-xxx m pd780022ycw(a)-xxx, 780023ycw(a)-xxx, 780024ycw(a)-xxx m pd780021ygc(a)-xxx-ab8, 780022ygc(a)-xxx-ab8, 780023ygc(a)-xxx-ab8 m pd780024ygc(a)-xxx-ab8, 780021ygk(a)-xxx-8a8, 780022ygk(a)-xxx-8a8 m pd780023ygk(a)-xxx-8a8, 780024ygk(a)-xxx-8a8, 780031cw-xxx m pd780032cw-xxx, 780033cw-xxx, 780034cw-xxx, 780031gc-xxx-ab8 m pd780032gc-xxx-ab8, 780033gc-xxx-ab8, 780034gc-xxx-ab8 m pd780031gk-xxx-8a8, 780032gk-xxx-8a8, 780033gk-xxx-8a8 m pd780034gk-xxx-8a8, 780031cw(a)-xxx, 780032cw(a)-xxx m pd780033cw(a)-xxx, 780034cw(a)-xxx, 780031gc(a)-xxx-ab8 m pd780032gc(a)-xxx-ab8, 780033gc(a)-xxx-ab8, 780034gc(a)-xxx-ab8 m pd780031gk(a)-xxx-8a8, 780032gk(a)-xxx-8a8, 780033gk(a)-xxx-8a8 m pd780034gk(a)-xxx-8a8, 780031ycw-xxx, 780032ycw-xxx, 780033ycw-xxx m pd780034ycw-xxx, 780031ygc-xxx-ab8, 780032ygc-xxx-ab8 m pd780033ygc-xxx-ab8, 780034ygc-xxx-ab8, 780031ygk-xxx-8a8 m pd780032ygk-xxx-8a8, 780033ygk-xxx-8a8, 780034ygk-xxx-8a8 m pd780031ycw(a)-xxx, 780032ycw(a)-xxx, 780033ycw(a)-xxx m pd780034ycw(a)-xxx, 780031ygc(a)-xxx-ab8, 780032ygc(a)-xxx-ab8 m pd780033ygc(a)-xxx-ab8, 780034ygc(a)-xxx-ab8, 780031ygk(a)-xxx-8a8 m pd780032ygk(a)-xxx-8a8, 780033ygk(a)-xxx-8a8, 780034ygk(a)-xxx-8a8
5 the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the application circuits and their parameters are for reference only and are not intended for use in actual design.
6 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j97. 8
7 major revisions in this edition page description p.87 addition of caution regarding setting values for memory size switching register to 5.1 memory spaces p.161, 162 change and addition of caution to 8.3 16-bit timer/event counter configuration (2) capture/ compare register00(cr00) , (3) capture/compare register01(cr01) p.163 change in figure 8-2 16-bit timer mode control register (tmc0) format p.164 addition of caution to figure 8-3 capture/compare control register 0 (crc0) format p.165 addition of note to figure 8-4 16-bit timer output control register (toc0) format p.166 change and addition of caution to figure 8-5 prescaler mode register 0 (prm0) format p.170 addition of caution to figure 8-10 control register settings for ppg output operation p.172, 174, 176, 177 revision of following timing charts in chapter 8 16-bit timer/event counter figure 8-13 timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) figure 8-16 timing of pulse width measurement operation with free-running counter (with both edges specified) figure 8-18 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) figure 8-20 timing of pulse width measurement operation by means of restart (with rising edge specified) p.178 addition of caution to 8.5.4 external event counter operation p.181 8.5.6 one-shot pulse output operation first sentence about prohibition of one-shot pulse output with external trigger completely changed p.186, 187 8.6 16-bit timer/event counter operating precautions revision in (7) operation of ovf0 flag addition of the following items (9) timer operation (10) capture operation (11) compare operation (12) edge detection p.230 revision of caution of 13.2 a/d converter configuration (2) a/d conversion result register (adcr0) p.245 revision in 13.5 a/d converter cautions (10) a/d conversion result register (adcr0) read operation p.248 revision of caution of 14.2 a/d converter configuration (2) a/d conversion result register (adcr0) p.260 revision in 14.5 a/d converter cautions (10) a/d conversion result register (adcr0) read operation p.289 addition of note to figure 17-2 serial interface (csim30) format p.297 revision of 18.3 registers to control serial interface (1) iic control register (iicc0) p.299, 300 revision of description of stt0 and spt0 flags in figure 18-3 iic control register (iicc0) format the mark shows major revised points.
8 [memo]
9 introduction readers this manual has been prepared for user engineers who understand the functions of the m pd780024, 780034, 780024y, and 780034y subseries and wish to design and develop application systems and programs for these devices. m pd780024 subseries : m pd780021, 780022, 780023, 780024 m pd780021(a), 780022(a), 780023(a), 780024(a) m pd780034 subseries : m pd780031, 780032, 780033, 780034, 78f0034 m pd780031(a), 780032(a), 780033(a), 780034(a) m pd780024y subseries : m pd780021y, 780022y, 780023y, 780024y m pd780021y(a), 780022y(a), 780023y(a), 780024y(a) m pd780034y subseries : m pd780031y, 780032y, 780033y, 780034y, 78f0034y m pd780031y(a), 780032y(a), 780033y(a), 780034y(a) purpose this manual is intended to provide users an understanding of the functions described in the organization below. organization the m pd780024, 780034, 780024y, and 780034y subseries manual is separated into two parts: this manual and the instructions edition (common to the 78k/0 series). m pd780024, 780034, 780024y, 780034y 78k/0 series subseries users manual users manual (this manual) instructions ? pin functions ? cpu functions ? internal block functions ? instruction set ? interrupt ? explanation of each instruction ? other on-chip peripheral functions
10 how to read this manual before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. ? for readers who use this as an (a) product: ? standard products differ from (a) products in their quality grade only. re-read the product name as indicated below if your products is an (a) product. m pd780021 ? m pd780021(a) m pd780021y ? m pd780021y(a) m pd780022 ? m pd780022(a) m pd780022y ? m pd780022y(a) m pd780023 ? m pd780023(a) m pd780023y ? m pd780023y(a) m pd780024 ? m pd780024(a) m pd780024y ? m pd780024y(a) m pd780031 ? m pd780031(a) m pd780031y ? m pd780031y(a) m pd780032 ? m pd780032(a) m pd780032y ? m pd780032y(a) m pd780033 ? m pd780033(a) m pd780033y ? m pd780033y(a) m pd780034 ? m pd780034(a) m pd780034y ? m pd780034y(a) ? to gain a general understanding of functions: ? read this manual in the order of the contents. ? how to interpret the register format: ? for the bit number enclosed in square, the bit name is defined as a reserved word in ra78k/0, and in cc78k/0, already defined in the header file named sfrbit.h. ? to check the details of a register when you know the register name. ? refer to appendix d. caution examples in this manual employ the standard quality grade for general electronics. when using examples in this manual for the standard quality grade, review the quality grade of each part and/or circuit actually used.
11 chapter organization this manual divides the descriptions for the subseries into different chapters as shown below. read only the chapters related to the device you use. chapter m pd780024 m pd780034 m pd780024y m pd780034y subseries subseries subseries subseries chapter 1 outline ( m pd780024, 780034 subseries) chapter 2 outline ( m pd780024y, 780034y subseries) chapter 3 pin function ( m pd780024, 780034 subseries) chapter 4 pin function ( m pd780024y, 780034y subseries) chapter 5 cpu architecture chapter 6 port functions chapter 7 clock generator chapter 8 16-bit timer/event counter chapter 9 8-bit timer/event counter chapter 10 watch timer chapter 11 watchdog timer chapter 12 clock output/buzzer output control circuit chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) chapter 15 serial interface chapter 16 serial interface (uart0) chapter 17 serial interface (sio3) chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) chapter 19 interrupt functions chapter 20 external device expansion functions chapter 21 standby function chapter 22 reset function chapter 23 m pd78f0034, 78f0034y chapter 24 instruction set
12 differences between m pd780024, 780034 subseries and m pd780024y, 780034y subseries: the m pd780024, 780034 subseries and m pd780024y, 780034y subseries are different in the following functions of the serial interface channel 0. serial interface m pd780024, 780034 subseries m pd780024y, 780034y subseries 3-wire serial i/o mode 2 ch (sio30, sio31) 1 ch (sio30 only) uart mode 1 ch 1 ch i 2 c bus mode not supported 1 ch legend data representation weight : high digits on the left and low digits on the right active low representations : (line over the pin and signal names) note : description of note in the text. caution : information requiring particular attention remarks : additional explanatory material numerical representations : binary or b decimal hexadecimal h
13 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? related documents for m pd780024 subseries document name document no. japanese english m pd780021, 780022, 780023, 780024 data sheet u12299j u12299e m pd780024, 780034, 780024y, 780034y subseries users manual u12022j this manual 78k/0 series users manual-instructions u12326j u12326e 78k/0 series instruction application table u10903j 78k/0 series instruction set u10904j m pd780034 subseries special function register table to be prepared 78k/0 series application note basics (i) u12704j iea-1288 ? related documents for m pd780024y subseries document name document no. japanese english m pd780021y, 780022y, 780023y, 780024y data sheet u12165j u12165e m pd780024, 780034, 780024y, 780034y subseries users manual u12022j this manual 78k/0 series users manual-instructions u12326j u12326e 78k/0 series instruction application table u10903j 78k/0 series instruction set u10904j m pd780034y subseries special function register table to be prepared 78k/0 series application note basics (i) u12704j iea-1288 caution the above documents are subject to change without prior notice. be sure to use the latest version document when starting design.
14 ? related documents for m pd780034 subseries document name document no. japanese english m pd780031, 780032, 780033, 780034 data sheet u12300j u12300e m pd78f0034 data sheet u11993j u11993e m pd780024, 780034, 780024y, 780034y subseries users manual u12022j this manual 78k/0 series users manual-instructions u12326j u12326e 78k/0 series instruction applications table u10903j 78k/0 series instruction set u10904j m pd780034 subseries special function register table to be prepared 78k/0 series application note basics (i) u12704j iea-1288 ? related documents for m pd780034y subseries document name document no. japanese english m pd780031y, 780032y, 780033y, 780034y data sheet u12166j u12166e m pd78f0034y data sheet u11994j u11994e m pd780024, 780034, 780024y, 780034y subseries users manual u12022j this manual 78k/0 series users manual-instructions u12326j u12326e 78k/0 series instruction applications table u10903j 78k/0 series instruction set u10904j m pd780034y subseries special function register table to be prepared 78k/0 series application note basics (i) u12704j iea-1288 caution the above documents are subject to change without prior notice. be sure to use the latest version document when starting design.
15 ? related documents for development tool (users manuals) document name document no. japanese english ra78k0 assembler package operation u11802j u11802e language u11801j u11801e structured assembly language u11789j u11789e ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e cc78k0 c compiler application note programming know-how u13034j eea-1208 cc78k series library source file u12322j ie-78k0-ns to be prepared to be prepared ie-78001-r-a to be prepared to be prepared ie-78k0-r-ex1 to be prepared to be prepared ie-780034-ns-em1 to be prepared to be prepared ep-78240 eeu-986 u10332e ep-78012gk-r eeu-5012 eeu-1538 sm78k0 system simulator windows tm based reference u10181j u10181e sm78k series system simulator external part user open interface u10092j u10092e id78k0-ns integrated debugger pc based reference u12900j to be prepared id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e ? related documents for embedded software (users manual) document name document no. japanese english 78k/0 series real-time os basics u11537j u11537e installation u11536j u11536e 78k/0 series os mx78k0 basics u12257j u12257e caution the above documents are subject to change without prior notice. be sure to use the latest version document when starting design.
16 ? other documents document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e guide to quality assurance for semiconductor devices mei-1202 microcomputer related product series guide - third party manufacturers u11416j caution the above documents are subject to change without prior notice. be sure to use the latest version document when starting design.
17 contents chapter 1 outline ( m pd780024, 780034 subseries) ......................................................... 31 1.1 features .................................................................................................................... ............ 31 1.2 applications ................................................................................................................ ......... 32 1.3 ordering information ........................................................................................................ ... 33 1.4 quality grade ............................................................................................................... ........ 35 1.5 pin configuration (top view) .............................................................................................. 37 1.6 78k/0 series expansion ...................................................................................................... 41 1.7 block diagram ............................................................................................................... ....... 43 1.8 outline of function ......................................................................................................... ..... 44 1.9 difference between standard grade and special grade .................................................. 45 1.10 mask options ............................................................................................................... ........ 45 chapter 2 outline ( m pd780024y, 780034y subseries) .................................................... 47 2.1 features ................................................................................................................... ............ 47 2.2 applications ................................................................................................................ ......... 48 2.3 ordering information ........................................................................................................ ... 49 2.4 quality grade ............................................................................................................... ........ 51 2.5 pin configuration (top view) .............................................................................................. 53 2.6 78k/0 series expansion ...................................................................................................... 57 2.7 block diagram ............................................................................................................... ....... 59 2.8 outline of function ......................................................................................................... ..... 60 2.9 difference between standard grade and special grade .................................................. 61 2.10 mask options ............................................................................................................... ........ 61 chapter 3 pin function ( m pd780024, 780034 subseries) .............................................. 63 3.1 pin function list ........................................................................................................... ....... 63 3.2 description of pin functions .............................................................................................. 66 3.2.1 p00 to p03 (port 0) ....................................................................................................... ............. 66 3.2.2 p10 to p17 (port 1) ....................................................................................................... ............. 66 3.2.3 p20 to p25 (port 2) ....................................................................................................... ............. 67 3.2.4 p30 to p36 (port 3) ....................................................................................................... ............. 67 3.2.5 p40 to p47 (port 4) ....................................................................................................... ............. 68 3.2.6 p50 to p57 (port 5) ....................................................................................................... ............. 68 3.2.7 p64 to p67 (port 6) ....................................................................................................... ............. 68 3.2.8 p70 to p75 (port 7) ....................................................................................................... ............. 69 3.2.9 av ref ............................................................................................................................... ........... 69 3.2.10 av dd ............................................................................................................................... ............ 69 3.2.11 av ss ............................................................................................................................... ............. 69 3.2.12 reset .................................................................................................................... ................... 70 3.2.13 x1 and x2 ................................................................................................................ .................. 70 3.2.14 xt1 and xt2 .............................................................................................................. ................ 70 3.2.15 v dd0 and v dd1 ............................................................................................................................. 70
18 3.2.16 v ss0 and v ss1 ............................................................................................................................. 70 3.2.17 v pp (flash memory versions only) ............................................................................................... 70 3.2.18 ic (mask rom version only) ............................................................................................... ....... 70 3.3 pin input/output circuits and recommended connection of unused pins ................... 71 chapter 4 pin function ( m pd780024y, 780034y subseries) ........................................ 75 4.1 pin function list ........................................................................................................... ....... 75 4.2 description of pin functions .............................................................................................. 78 4.2.1 p00 to p03 (port 0) ....................................................................................................... ............. 78 4.2.2 p10 to p17 (port 1) ....................................................................................................... ............. 78 4.2.3 p20 to p25 (port 2) ....................................................................................................... ............. 79 4.2.4 p30 to p36 (port 3) ....................................................................................................... ............. 79 4.2.5 p40 to p47 (port 4) ....................................................................................................... ............. 80 4.2.6 p50 to p57 (port 5) ....................................................................................................... ............. 80 4.2.7 p64 to p67 (port 6) ....................................................................................................... ............. 80 4.2.8 p70 to p75 (port 7) ....................................................................................................... ............. 81 4.2.9 av ref ............................................................................................................................... ........... 81 4.2.10 av dd ............................................................................................................................... ............ 81 4.2.11 av ss ............................................................................................................................... ............. 81 4.2.12 reset .................................................................................................................... ................... 82 4.2.13 x1 and x2 ................................................................................................................ .................. 82 4.2.14 xt1 and xt2 .............................................................................................................. ................ 82 4.2.15 v dd0 , v dd1 ............................................................................................................................... .... 82 4.2.16 v ss0 , v ss1 ............................................................................................................................... .... 82 4.2.17 v pp (flash memory versions only) ............................................................................................... 82 4.2.18 ic (mask rom version only) ............................................................................................... ....... 82 4.3 pin input/output circuits and recommended connection of unused pins ................... 83 chapter 5 cpu architecture ................................................................................................ 8 7 5.1 memory spaces ............................................................................................................... ..... 87 5.1.1 internal program memory space ............................................................................................. ... 92 5.1.2 internal data memory space ................................................................................................ ....... 94 5.1.3 special function register (sfr) area ...................................................................................... .94 5.1.4 external memory space ..................................................................................................... ........ 94 5.1.5 data memory addressing .................................................................................................... ....... 95 5.2 processor registers ........................................................................................................ .... 100 5.2.1 control registers ......................................................................................................... ................ 100 5.2.2 general registers ......................................................................................................... ............... 103 5.2.3 special function register (sfr) ........................................................................................... ..... 104 5.3 instruction address addressing ........................................................................................ 108 5.3.1 relative addressing ....................................................................................................... ............. 108 5.3.2 immediate addressing ...................................................................................................... .......... 109 5.3.3 table indirect addressing ................................................................................................. .......... 110 5.3.4 register addressing ....................................................................................................... ............ 111 5.4 operand address addressing ............................................................................................ 112 5.4.1 implied addressing ........................................................................................................ ............. 112
19 5.4.2 register addressing ....................................................................................................... ............ 113 5.4.3 direct addressing ......................................................................................................... .............. 114 5.4.4 short direct addressing ................................................................................................... ........... 115 5.4.5 special-function register (sfr) addressing ............................................................................... 1 17 5.4.6 register indirect addressing .............................................................................................. ......... 118 5.4.7 based addressing .......................................................................................................... ............ 119 5.4.8 based indexed addressing .................................................................................................. ....... 120 5.4.9 stack addressing .......................................................................................................... .............. 120 chapter 6 port functions ................................................................................................... .. 121 6.1 port functions .............................................................................................................. ........ 121 6.2 port configuration .......................................................................................................... ..... 124 6.2.1 port 0 .................................................................................................................... ...................... 124 6.2.2 port 1 .................................................................................................................... ...................... 125 6.2.3 port 2 .................................................................................................................... ...................... 126 6.2.4 port 3 ( m pd780024, 780034 subseries) .................................................................................... 127 6.2.5 port 3 ( m pd780024y, 780034y subseries) ................................................................................ 129 6.2.6 port 4 .................................................................................................................... ...................... 132 6.2.7 port 5 .................................................................................................................... ...................... 133 6.2.8 port 6 .................................................................................................................... ...................... 134 6.2.9 port 7 .................................................................................................................... ...................... 135 6.3 port function control registers ........................................................................................ 136 6.4 port function operations .................................................................................................... 140 6.4.1 writing to input/output port .............................................................................................. ........... 140 6.4.2 reading from input/output port ............................................................................................ ....... 140 6.4.3 operations on input/output port ........................................................................................... ....... 140 6.5 selection of mask option .................................................................................................... 141 chapter 7 clock generator ................................................................................................ 14 3 7.1 clock generator functions ................................................................................................. 14 3 7.2 clock generator configuration .......................................................................................... 143 7.3 clock generator control register ...................................................................................... 145 7.4 system clock oscillator ..................................................................................................... . 147 7.4.1 main system clock oscillator .............................................................................................. ......... 147 7.4.2 subsystem clock oscillator ................................................................................................ ......... 148 7.4.3 scaler .................................................................................................................... ..................... 151 7.4.4 when no subsystem clocks are used ......................................................................................... 151 7.5 clock generator operations ............................................................................................... 15 2 7.5.1 main system clock operations .............................................................................................. ...... 153 7.5.2 subsystem clock operations ................................................................................................ ...... 154 7.6 changing system clock and cpu clock settings ............................................................ 154 7.6.1 time required for switchover between system clock and cpu clock ......................................... 154 7.6.2 system clock and cpu clock switching procedure .................................................................... 156
20 chapter 8 16-bit timer/event counter ............................................................................. 157 8.1 outline of timer integrated in m pd780024, 780034, 780024y, 780034y subseries ........ 157 8.2 16-bit timer/event counter functions .............................................................................. 158 8.3 16-bit timer/event counter configuration ........................................................................ 160 8.4 registers to control 16-bit timer/event counter ............................................................. 162 8.5 16-bit timer/event counter operations ............................................................................. 168 8.5.1 interval timer operations ................................................................................................. ............ 168 8.5.2 ppg output operations ..................................................................................................... .......... 170 8.5.3 pulse width measurement operations ........................................................................................ 171 8.5.4 external event counter operation .......................................................................................... ..... 178 8.5.5 square-wave output operation .............................................................................................. ..... 179 8.5.6 one-shot pulse output operation ........................................................................................... ..... 181 8.6 16-bit timer/event counter operating precautions ......................................................... 184 chapter 9 8-bit timer/event counter ................................................................................ 189 9.1 8-bit timer/event counter functions ................................................................................ 189 9.2 8-bit timer/event counter configurations ........................................................................ 191 9.3 registers to control 8-bit timer/event counter ............................................................... 192 9.4 8-bit timer/event counter operations ............................................................................... 196 9.4.1 8-bit interval timer operation ............................................................................................ ........... 196 9.4.2 external event counter operation .......................................................................................... ..... 200 9.4.3 square-wave output (8-bit resolution) operation ........................................................................ 201 9.4.4 8-bit pwm output operation ................................................................................................ ....... 202 9.4.5 interval timer (16-bit) operations ........................................................................................ ........ 205 9.5 8-bit timer/event counters cautions ................................................................................ 206 chapter 10 watch timer .................................................................................................... .... 209 10.1 watch timer functions ...................................................................................................... . 209 10.2 watch timer configuration ................................................................................................. 2 10 10.3 register to control watch timer ........................................................................................ 211 10.4 watch timer operations ..................................................................................................... 212 10.4.1 watch timer operation .................................................................................................... ............ 212 10.4.2 interval timer operation ................................................................................................. ............. 212 chapter 11 watchdog timer ................................................................................................ 2 15 11.1 watchdog timer functions ................................................................................................. 21 5 11.2 watchdog timer configuration .......................................................................................... 217 11.3 registers to control the watchdog timer ......................................................................... 217 11.4 watchdog timer operations ............................................................................................... 221 11.4.1 watchdog timer operation ................................................................................................. ......... 221 11.4.2 interval timer operation ................................................................................................. ............. 222
21 chapter 12 clock output/buzzer output control circuits .................................. 223 12.1 clock output/buzzer output control circuit functions .................................................. 223 12.2 clock output/buzzer output control circuit configuration ............................................ 224 12.3 register to control clock output/buzzer output control circuit ................................... 224 12.4 clock output/buzzer output control circuit operations ................................................. 227 12.4.1 operation as clock output ................................................................................................ .......... 227 12.4.2 operation as buzzer output ............................................................................................... ......... 227 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) ............................... 229 13.1 a/d converter functions .................................................................................................... . 229 13.2 a/d converter configuration .............................................................................................. 23 0 13.3 registers to control a/d converter ................................................................................... 232 13.4 a/d converter operations ................................................................................................... 236 13.4.1 basic operations of a/d converter ........................................................................................ ...... 236 13.4.2 input voltage and conversion results ..................................................................................... ..... 238 13.4.3 a/d converter operation mode ............................................................................................. ...... 239 13.5 a/d converter cautions ..................................................................................................... . 242 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) ............................ 247 14.1 a/d converter functions .................................................................................................... . 247 14.2 a/d converter configuration .............................................................................................. 24 8 14.3 registers to control a/d converter ................................................................................... 249 14.4 a/d converter operation .................................................................................................... . 252 14.4.1 basic operations of a/d converter ........................................................................................ ...... 252 14.4.2 input voltage and conversion results ..................................................................................... ..... 254 14.4.3 a/d converter operation mode ............................................................................................. ...... 255 14.5 a/d converter cautions ..................................................................................................... . 257 chapter 15 serial interface outline ................................................................................ 261 chapter 16 serial interface (uart0) .................................................................................. 263 16.1 serial interface functions ................................................................................................. .. 263 16.2 serial interface configuration ............................................................................................. 264 16.3 registers to control serial interface .................................................................................. 265 16.4 serial interface operations ................................................................................................ . 269 16.4.1 operation stop mode ...................................................................................................... ............ 269 16.4.2 asynchronous serial interface (uart) mode ............................................................................. 269 16.4.3 infrared data transfer mode .............................................................................................. .......... 281 chapter 17 serial interface (sio3) ..................................................................................... 285 17.1 serial interface functions ................................................................................................. .. 286 17.2 serial interface configuration ............................................................................................. 287 17.3 register to control serial interface .................................................................................... 288
22 17.4 serial interface operations ................................................................................................ . 289 17.4.1 operation stop mode ...................................................................................................... ............ 289 17.4.2 3-wire serial i/o mode ................................................................................................... ............. 290 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) ............ 293 18.1 serial interface functions ................................................................................................. .. 293 18.2 serial interface configuration ............................................................................................. 296 18.3 registers to control serial interface .................................................................................. 297 18.4 i 2 c bus mode functions ..................................................................................................... 306 18.4.1 pin configuration ...................................................................................................... ................... 306 18.5 i 2 c bus definitions and control methods ......................................................................... 307 18.5.1 start conditions ......................................................................................................... ................. 307 18.5.2 addresses ................................................................................................................ .................. 308 18.5.3 transfer direction specification ......................................................................................... .......... 308 18.5.4 acknowledge (ack) signal ................................................................................................. ........ 309 18.5.5 stop condition ........................................................................................................... ................. 310 18.5.6 wait signal (wait) ....................................................................................................... ............... 311 18.5.7 i 2 c interrupt requests (intiic0) ................................................................................................. 313 18.5.8 interrupt request (intiic0) generation timing and wait control .................................................. 332 18.5.9 address match detection method ........................................................................................... .... 333 18.5.10 error detection ....................................................................................................... ................... 333 18.5.11 extension code ........................................................................................................ ................. 333 18.5.12 arbitration ........................................................................................................... ...................... 334 18.5.13 wake up function ...................................................................................................... ................ 335 18.5.14 communication reservation ............................................................................................. ........ 336 18.5.15 other cautions ........................................................................................................ .................. 338 18.5.16 communication operations .............................................................................................. ........ 339 18.6 timing charts .............................................................................................................. ......... 341 chapter 19 interrupt functions ........................................................................................ 349 19.1 interrupt function types ................................................................................................... .. 349 19.2 interrupt sources and configuration ................................................................................. 349 19.3 interrupt function control registers ................................................................................. 353 19.4 interrupt servicing operations ........................................................................................... 35 9 19.4.1 non-maskable interrupt request acknowledge operation ........................................................... 359 19.4.2 maskable interrupt acknowledge operation ................................................................................ 3 62 19.4.3 software interrupt request acknowledge operation .................................................................... 364 19.4.4 multiple interrupt servicing ............................................................................................. ............ 365 19.4.5 interrupt request hold ................................................................................................... .............. 368 chapter 20 external device expansion function .................................................... 369 20.1 external device expansion function ................................................................................. 369 20.2 external device expansion function control register .................................................... 372 20.3 external device expansion function timing .................................................................... 374 20.4 example of connection with memory ................................................................................ 379
23 chapter 21 standby function .............................................................................................. 38 1 21.1 standby function and configuration ................................................................................ 381 21.1.1 standby function ......................................................................................................... ............... 381 21.1.2 standby function control register ........................................................................................ ........ 382 21.2 standby function operations ............................................................................................. 383 21.2.1 halt mode ................................................................................................................ ................ 383 21.2.2 stop mode ................................................................................................................ ................ 386 chapter 22 reset function ................................................................................................. . 389 22.1 reset function ............................................................................................................. ........ 389 chapter 23 m pd78f0034, 78f0034y ............................................................................................ 393 23.1 memory size switching register ........................................................................................ 395 23.2 flash memory programming .............................................................................................. 396 23.2.1 selection of transmission method ......................................................................................... ..... 396 23.2.2 flash memory programming function ........................................................................................ . 397 23.2.3 flashpro ii connection ................................................................................................... ............. 397 chapter 24 instruction set ................................................................................................. . 399 24.1 legends used in operation list ......................................................................................... 400 24.1.1 operand identifiers and description methods ............................................................................. 4 00 24.1.2 description of operation column ........................................................................................ ...... 401 24.1.3 description of flag operation column ................................................................................... .... 401 24.2 operation list ............................................................................................................. .......... 402 24.3 instructions listed by addressing type ........................................................................... 410 appendix a differences between m pd78014h, 78018f, 780024, and 780034 subseries .......................................................................................... 415 appendix b development tools .......................................................................................... 417 b.1 language processing software ......................................................................................... 419 b.2 flash memory writing tools ............................................................................................... 420 b.3 debugging tools ............................................................................................................. ..... 421 b.3.1 hardware .................................................................................................................. .................. 421 b.3.2 software .................................................................................................................. ................... 423 b.4 system upgrade from former in-circuit emulator for 78k/0 series to ie-78001-r-a .... 425 appendix c embedded software ......................................................................................... 429 appendix d register index .................................................................................................. ... 433 d.1 register index (in alphabetical order with respect to register names) ....................... 433 d.2 register index (in alphabetical order with respect to register symbol) ..................... 436 appendix e revision history ................................................................................................. . 439
24 list of figures (1/5) figure no. title page 3-1 pin input/output circuit of list ............................................................................................ .............. 73 4-1 pin input/output circuit of list ............................................................................................ .............. 85 5-1 memory map ( m pd780021, 780031, 780021y, 780031y) ................................................................ 87 5-2 memory map ( m pd780022, 780032, 780022y, 780032y) ................................................................ 88 5-3 memory map ( m pd780023, 780033, 780023y, 780033y) ................................................................ 89 5-4 memory map ( m pd780024, 780034, 780024y, 780034y) ................................................................ 90 5-5 memory map ( m pd78f0034, 78f0034y) .......................................................................................... 91 5-6 data memory addressing ( m pd780021, 780031, 780021y, 780031y) ............................................. 95 5-7 data memory addressing ( m pd780022, 780032, 780022y, 780032y) ............................................. 96 5-8 data memory addressing ( m pd780023, 780033, 780023y, 780033y) ............................................. 97 5-9 data memory addressing ( m pd780024, 780034, 780024y, 780034y) ............................................. 98 5-10 data memory addressing ( m pd78f0034, 78f0034y) ...................................................................... 99 5-11 program counter format ..................................................................................................... ............. 100 5-12 program status word format ................................................................................................. .......... 100 5-13 stack pointer format ....................................................................................................... ................. 102 5-14 data to be saved to stack memory ........................................................................................... ....... 102 5-15 data to be reset from stack memory ......................................................................................... ...... 102 5-16 general register configuration ............................................................................................. ........... 103 6-1 port types .................................................................................................................. ....................... 121 6-2 p00 to p03 configurations ................................................................................................... ............. 125 6-3 p10 to p17 configurations ................................................................................................... ............. 125 6-4 p20 to p25 configurations ................................................................................................... ............. 126 6-5 p30 to p33 configurations ( m pd780024, 780034 subseries) .......................................................... 127 6-6 p34 to p36 configurations ( m pd780024, 780034 subseries) .......................................................... 128 6-7 p30 and p31 configurations ( m pd780024y, 780034y subseries) ................................................... 130 6-8 p32 and p33 configurations ( m pd780024y, 780034y subseries) ................................................... 130 6-9 p34 to p36 configurations ( m pd780024y, 780034y, subseries) ...................................................... 131 6-10 p40 to p47 configurations .................................................................................................. .............. 132 6-11 falling edge detection circuit block diagram ............................................................................... ... 132 6-12 p50 to p57 configurations .................................................................................................. .............. 133 6-13 p64 to p67 configurations .................................................................................................. .............. 134 6-14 p70 to p75 configurations .................................................................................................. .............. 135 6-15 port mode register (pm0, pm2 to pm7) format .............................................................................. 13 7 6-16 pull-up resistor option register (pu0, pu2 to pu7) format .......................................................... 139 7-1 clock generator block diagram ............................................................................................... ........ 144 7-2 subsystem clock feedback resistor ........................................................................................... .... 145 7-3 processor clock control register (pcc) format ............................................................................. 14 6 7-4 external circuit of main system clock oscillator ............................................................................ .. 147 7-5 external circuit of subsystem clock oscillator .............................................................................. ... 148 7-6 examples of incorrect oscillator connection ................................................................................. ... 149 7-7 main system clock stop function ............................................................................................. ....... 153 7-8 system clock and cpu clock switching ........................................................................................ .. 156
25 list of figures (2/5) figure no. title page 8-1 16-bit timer/event counter block diagram .................................................................................... .. 159 8-2 16-bit timer mode control register (tmc0) format ........................................................................ 163 8-3 capture/compare control register 0 (crc0) format ...................................................................... 164 8-4 16-bit timer output control register l (toc0) format .................................................................... 165 8-5 prescaler mode register 0 (prm0) format ..................................................................................... 166 8-6 port mode register 7 (pm7) format ........................................................................................... ...... 167 8-7 control register settings for interval timer operation ..................................................................... 1 68 8-8 interval timer configuration diagram ........................................................................................ ....... 169 8-9 timing of interval timer operation .......................................................................................... .......... 169 8-10 control register settings for ppg output operation ....................................................................... 17 0 8-11 control register settings for pulse width measurement with free-running counter and one capture register ....................................................................................................... ......... 171 8-12 configuration diagram for pulse width measurement by free-running counter ............................ 172 8-13 timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) ........................................................................................... .... 172 8-14 control register settings for measurement of two pulse widths with free-running counter ........ 173 8-15 capture operation with rising edge specified ............................................................................... .. 174 8-16 timing of pulse width measurement operation with free-running counter (with both edges specified) .................................................................................................... .......... 174 8-17 control register settings for pulse width measurement with free-running counter and two capture registers .......................................................................................................... ........... 175 8-18 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) ......................................................................................... .... 176 8-19 control register settings for pulse width measurement by means of restart ................................ 177 8-20 timing of pulse width measurement operation by means of restart (with rising edge specified) ................................................................................................... .......... 177 8-21 control register settings in external event counter mode .............................................................. 178 8-22 external event counter configuration diagram ............................................................................... . 179 8-23 external event counter operation timings (with rising edge specified) ........................................ 179 8-24 control register settings in square-wave output mode ................................................................. 180 8-25 square-wave output operation timing ........................................................................................ .... 181 8-26 control register settings for one-shot pulse output operation using software trigger ................ 182 8-27 timing of one-shot pulse output operation using software trigger ............................................... 183 8-28 16-bit timer register start timing ......................................................................................... ........... 184 8-29 timings after change of compare register during timer count operation .................................... 184 8-30 capture register data retention timing ..................................................................................... ..... 185 8-31 operation timing of ovf0 flag .............................................................................................. .......... 186 9-1 8-bit timer/event counter 50 block diagram .................................................................................. . 190 9-2 8-bit timer/event counter 51 block diagram .................................................................................. . 190 9-3 timer clock select register 50 (tcl50) format .............................................................................. 1 92 9-4 timer clock select register 51 (tcl51) format .............................................................................. 1 93 9-5 8-bit timer mode control register 5n (tmc5n) format ................................................................... 194 9-6 port mode register 7 (pm7) format ........................................................................................... ...... 195 9-7 interval timer operation timings ............................................................................................ .......... 197
26 list of figures (3/5) figure no. title page 9-8 external event counter operation timings (with rising edge specified) ........................................ 200 9-9 square-wave output operation timing ......................................................................................... ... 201 9-10 pwm output operation timing ................................................................................................ ......... 203 9-11 timing of operation by change of cr5n ...................................................................................... .... 204 9-12 16-bit resolution cascade connection mode .................................................................................. 206 9-13 8-bit counters start timing ................................................................................................ ............... 206 9-14 timing after compare register transition during timer count operation ........................................ 207 10-1 watch timer block diagram .................................................................................................. ........... 209 10-2 watch timer mode control register (wtm) format ........................................................................ 211 10-3 operation timing of watch timer/interval timer ............................................................................. .. 213 11-1 watchdog timer block diagram ............................................................................................... ........ 215 11-2 watchdog timer clock select register (wdcs) format .................................................................. 218 11-3 watchdog timer mode register (wdtm) format ............................................................................ 219 11-4 oscillation stabilization time select register (osts) format ......................................................... 220 12-1 clock output/buzzer output control circuit block diagram ............................................................. 223 12-2 clock output selection register (cks) format ............................................................................... . 225 12-3 port mode register 7 (pm7) format .......................................................................................... ....... 226 12-4 remote control output application example .................................................................................. . 227 13-1 8-bit a/d converter block diagram .......................................................................................... ......... 229 13-2 a/d converter mode register (adm0) format ................................................................................. 2 33 13-3 analog input channel specification register (ads0) format .......................................................... 234 13-4 external interrupt rising edge enable register (egp), internal interrupt falling edge enable register (egn) format .......................................................................................................... ........... 235 13-5 basic operation of 8-bit a/d converter ..................................................................................... ....... 237 13-6 relationship between analog input voltage and a/d conversion result ......................................... 238 13-7 a/d conversion by hardware start (when falling edge is specified) ............................................. 240 13-8 a/d conversion by software start ........................................................................................... ......... 241 13-9 example of method of reducing current dissipation in standby mode ........................................... 242 13-10 analog input pin connection ............................................................................................... ............. 243 13-11 a/d conversion end interrupt request generation timing .............................................................. 244 13-12 serving av dd pins .......................................................................................................................... ... 245 14-1 10-bit a/d converter block diagram ......................................................................................... ....... 247 14-2 a/d converter mode register (adm0) format ................................................................................. 2 50 14-3 analog input channel specification register (ads0) format .......................................................... 251 14-4 external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) format .......................................................................................................... ........... 251 14-5 basic operation of 10-bit a/d converter .................................................................................... ...... 253 14-6 relationship between analog input voltage and a/d conversion result ......................................... 254 14-7 a/d conversion by hardware start (when falling edge is specified) ............................................. 255 14-8 a/d conversion by software start ........................................................................................... ......... 256
27 list of figures (4/5) figure no. title page 14-9 example of method of reducing current consumption in standby mode ....................................... 257 14-10 analog input pin connection ............................................................................................... ............. 258 14-11 a/d conversion end interrupt request generation timing .............................................................. 259 14-12 av dd pin connection ................................................................................................................ ........ 260 16-1 serial interface (uart0) block diagram ..................................................................................... ..... 263 16-2 asynchronous serial interface mode register (asim0) format ....................................................... 266 16-3 asynchronous serial interface status register (asis0) format ...................................................... 267 16-4 baud rate generator control register (brgc0) format ................................................................ 268 16-5 error tolerance (when k = 0), including sampling errors ................................................................. 275 16-6 format of transmit/receive data in asynchronous serial interface ................................................ 276 16-7 timing of asynchronous serial interface transmit completion interrupt request ............................ 278 16-8 timing of asynchronous serial interface receive completion interrupt request ............................ 279 16-9 receive error timing ....................................................................................................... ................. 280 16-10 data format comparison between infrared data transfer mode and uart mode ......................... 281 17-1 serial interface (sio30) block diagram ..................................................................................... ....... 286 17-2 serial operation mode register 30 (csim30) format ...................................................................... 288 17-3 timing of 3-wire serial i/o mode ........................................................................................... ........... 291 18-1 serial interface (iic0) block diagram ...................................................................................... ......... 294 18-2 serial bus configuration example using i 2 c bus ............................................................................. 295 18-3 iic control register (iicc0) format ........................................................................................ ......... 298 18-4 iic status register (iics0) format ......................................................................................... .......... 301 18-5 iic clock select register (iiccl0) format .................................................................................. ..... 304 18-6 pin configuration diagram .................................................................................................. .............. 306 18-7 i 2 c buss serial data transfer timing ............................................................................................ ... 307 18-8 start conditions ........................................................................................................... ..................... 307 18-9 address .................................................................................................................... ......................... 308 18-10 transfer direction specification .......................................................................................... .............. 308 18-11 ack signal ................................................................................................................ ........................ 309 18-12 stop condition ............................................................................................................ ...................... 310 18-13 wait signal ............................................................................................................... ......................... 311 18-14 arbitration timing example ................................................................................................ ............... 334 18-15 communication reservation timing .......................................................................................... ....... 337 18-16 timing for accepting communication reservations ......................................................................... 33 7 18-17 communication reservation protocol ........................................................................................ ...... 338 18-18 master operation flow chart ............................................................................................... ............. 339 18-19 slave operation flow chart ................................................................................................ .............. 340 18-20 example of master to slave communication (when 9-clock wait is selected for both master and slave) ..................................................................................................................... .................... 342 18-21 example of slave to master communication (when 9-clock wait is selected for both master and slave) ..................................................................................................................... .................... 345 19-1 basic configuration of interrupt function .................................................................................. ....... 351 19-2 interrupt request flag register (if0l, if0h, if1l) format .............................................................. 354
28 list of figures (5/5) figure no. title page 19-3 interrupt mask flag register (mk0l, mk0h, mk1l) format ............................................................ 355 19-4 priority specify flag register (pr0l, pr0h, pr1l) format ............................................................ 356 19-5 external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) format .......................................................................................................... ........... 357 19-6 program status word format ................................................................................................. .......... 358 19-7 non-maskable interrupt request generation to acknowledge flowchart ........................................ 360 19-8 non-maskable interrupt request acknowledge timing .................................................................... 360 19-9 non-maskable interrupt request acknowledge operation ............................................................... 361 19-10 interrupt request acknowledge processing algorithm ..................................................................... 363 19-11 interrupt request acknowledge timing (minimum time) ................................................................. 364 19-12 interrupt request acknowledge timing (maximum time) ................................................................ 364 19-13 multiple interrupt examples ............................................................................................... ............... 366 19-14 interrupt request hold .................................................................................................... .................. 368 20-1 external map when using external device function ........................................................................ 370 20-2 memory expansion mode register (mem) format .......................................................................... 372 20-3 memory expansion wait setting register (mm) format ................................................................... 373 20-4 instruction fetch from external memory ..................................................................................... ...... 375 20-5 external memory read timing ................................................................................................ ......... 376 20-6 external memory write timing ............................................................................................... ........... 377 20-7 external memory read modify write timing ................................................................................... .. 378 20-8 connection example of m pd780024 and memory ............................................................................ 379 21-1 oscillation stabilization time select register (osts) format ......................................................... 382 21-2 halt mode clear upon interrupt request generation .................................................................... 384 21-3 halt mode release by reset input ........................................................................................... ... 385 21-4 stop mode release by interrupt request generation .................................................................... 387 21-5 stop mode release by reset input ........................................................................................... .. 388 22-1 reset function block diagram ............................................................................................... .......... 389 22-2 timing of reset by reset input ............................................................................................. ......... 390 22-3 timing of reset due to watchdog timer overflow ............................................................................ 3 90 22-4 timing of reset in stop mode by reset input .............................................................................. 39 0 23-1 memory size switching register (ims) format ................................................................................ 395 23-2 transmission method selection format ....................................................................................... .... 396 23-3 connection of flashpro ii using 3-wire serial i/o method ............................................................... 397 23-4 flashpro ii connection using uart method ................................................................................... . 398 23-5 flashpro ii connection using i 2 c bus method .................................................................................. 398 23-6 flashpro ii connection using pseudo 3-wire serial i/o ................................................................... 398 b-1 development tool configuration. ............................................................................................. ......... 417 b-2 ev-9200gc-64 drawing (for reference only) ................................................................................... 426 b-3 ev-9200gc-64 footprints (for reference only) ................................................................................ 427 b-4 tgk-064sbw drawing (for reference only) .................................................................................... 4 28
29 list of tables (1/2) table no. title page 1-1 mask options of mask rom versions ........................................................................................... ... 45 2-1 mask options of mask rom versions ........................................................................................... ... 61 3-1 pin input/output circuit types .............................................................................................. ............ 71 4-1 pin input/output circuit types .............................................................................................. ............ 83 5-1 internal rom capacity ....................................................................................................... .............. 92 5-2 vector table ................................................................................................................ ...................... 93 5-3 internal high-speed ram capacity ............................................................................................ ...... 94 5-4 internal high-speed ram area ................................................................................................ ........ 101 5-5 special function register list .............................................................................................. ............ 105 6-1 port functions ( m pd780024, 780034 subseries) ............................................................................. 122 6-2 port functions ( m pd780024y, 780034y subseries) ......................................................................... 123 6-3 port configuration .......................................................................................................... ................... 124 6-4 pull-up resistor of port 3 ( m pd780024, 780034 subseries) ............................................................ 127 6-5 pull-up resistor of port 3 ( m pd780024y, 780034y subseries) ........................................................ 129 6-6 comparison between mask rom version and flash memory version ............................................ 141 7-1 clock generator configuration ............................................................................................... .......... 143 7-2 relationship of cpu clock and min. instruction execution time ..................................................... 147 7-3 maximum time required for cpu clock switchover ....................................................................... 155 8-1 timer/event counter operations .............................................................................................. ........ 158 8-2 16-bit timer/event counter configuration .................................................................................... .... 160 8-3 ti00/to0/p70 pin valid edge and capture/compare register capture trigger .............................. 161 8-4 ti01/p71 pin valid edge and capture/compare register capture trigger ...................................... 161 9-1 8-bit timer/event counters configurations ................................................................................... ... 191 10-1 interval timer interval time ............................................................................................... ............... 210 10-2 watch timer configuration .................................................................................................. ............. 210 10-3 interval timer interval time ............................................................................................... ............... 212 11-1 watchdog timer runaway detection times ..................................................................................... 216 11-2 interval times ............................................................................................................. ....................... 216 11-3 watchdog timer configuration ............................................................................................... .......... 217 11-4 watchdog timer runaway detection time ...................................................................................... . 221 11-5 interval timer interval time ............................................................................................... ............... 222 12-1 configuration of clock output/buzzer output control circuits ......................................................... 224 13-1 a/d converter configuration ................................................................................................ ............. 230
30 list of tables (2/2) table no. title page 14-1 a/d converter configuration ............................................................................................... ............. 248 15-1 differences between m pd780024, 780034 subseries and m pd780024y, 780034y subseries ........ 261 16-1 serial interface (uart0) configuration ..................................................................................... ....... 264 16-2 relationship between 5-bit counters source clock and n value .................................................. 273 16-3 relationship between main system clock and baud rate ............................................................... 274 16-4 causes of receive errors ................................................................................................... .............. 280 16-5 bit rate and pulse width values ............................................................................................ .......... 282 17-1 sio30 and sio31 naming differences ......................................................................................... .... 285 17-2 serial interface (sio30) configuration ..................................................................................... ......... 287 18-1 serial interface (iic0) configuration ...................................................................................... ........... 296 18-2 intiic0 timing and wait control ............................................................................................ .......... 332 18-3 extension code bit definitions ............................................................................................. ............ 333 18-4 status during arbitration and interrupt request generation timing ................................................. 335 18-5 wait periods ............................................................................................................... ....................... 336 19-1 interrupt source list ...................................................................................................... ................... 350 19-2 flags corresponding to interrupt request sources ......................................................................... 35 3 19-3 times from generation of maskable interrupt until servicing ........................................................... 362 19-4 interrupt request enabled for multiple interrupt during interrupt servicing ...................................... 365 20-1 pin functions in external memory expansion mode ........................................................................ 369 20-2 state of port 4 to 6 pins in external memory expansion mode ........................................................ 369 21-1 halt mode operating statuses .............................................................................................. ........ 383 21-2 operation after halt mode release ......................................................................................... ...... 385 21-3 stop mode operating status ................................................................................................ ......... 386 21-4 operation after stop mode release ......................................................................................... ..... 388 22-1 hardware statuses after reset .............................................................................................. ........... 391 23-1 differences among m pd78f0034 and mask rom versions ............................................................. 394 23-2 memory size switching register settings .................................................................................... .... 395 23-3 transmission method list ................................................................................................... .............. 396 23-4 main functions of flash memory programming ............................................................................... 39 7 24-1 operand identifiers and description methods ................................................................................ .. 400 a-1 major differences between m pd78014h, 78018f, 780024, and 780034 subseries ......................... 415
31 chapter 1 outline ( m pd780024, 780034 subseries) 1.1 features ? internal memory type program memory data memory part number (rom/flash memory) (high-speed ram) m pd780021, 780031 8 kbytes 512 bytes m pd780022, 780032 16 kbytes m pd780023, 780033 24 kbytes 1024 bytes m pd780024, 780034 32 kbytes m pd78f0034 32 kbytes note 1024 bytes note note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register (ims). ? external memory expansion space: 64 kbytes ? minimum instruction execution time changeable from high speed (0.24 m s: @ 8.38-mhz operation with main system clock) to ultra-low speed (122 m s: @ 32.768-khz operation with subsystem clock) ? instruction set suited to system control ? bit manipulation possible in all address spaces ? multiply and divide instructions ? fifty-one i/o ports: (four n-ch open-drain ports) ? 8-bit resolution a/d converter : 8 channels ( m pd780024 subseries only) ? 10-bit resolution a/d converter : 8 channels ( m pd780034 subseries only) ? serial interface : 3 channels ? 3-wire serial i/o mode : 2 channels ? uart mode : 1 channel ? timer: five channels ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel ? vectored interrupts: 20 ? two types of on-chip clock oscillators (main system clock and subsystem clock) ? power supply voltage: v dd = 1.8 to 5.5 v (other than m pd78f0034) v dd = 2.7 to 5.5 v ( m pd78f0034 only)
32 chapter 1 outline ( m pd780024, 780034 subseries) 1.2 applications m pd780021, 780022, 780023, 780024 m pd780031, 780032, 780033, 780034, 78f0034 home electric appliances, pagers, av equipment, car audios, car electric equipment, office automation equipment, etc. m pd780021(a), 780022(a), 780023(a), 780024(a) m pd780031(a), 780032(a), 780033(a), 780034(a) control of transportation equipment, gas detection breakers, safety devices, etc.
33 chapter 1 outline ( m pd780024, 780034 subseries) 1.3 ordering information (1) m pd780024 subseries part number package internal rom m pd780021cw- 64-pin plastic shrink dip (750 mils) mask rom m pd780021gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780021gk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780022cw- 64-pin plastic shrink dip (750 mils) mask rom m pd780022gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780022gk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780023cw- 64-pin plastic shrink dip (750 mils) mask rom m pd780023gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780023gk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780024cw- 64-pin plastic shrink dip (750 mils) mask rom m pd780024gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780024gk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780021cw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780021gc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780021gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780022cw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780022gc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780022gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780023cw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780023gc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780023gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780024cw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780024gc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780024gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom remark indicates rom code suffix.
34 chapter 1 outline ( m pd780024, 780034 subseries) (2) m pd780034 subseries part number package internal rom m pd780031cw- 64-pin plastic shrink dip (750 mils) mask rom m pd780031gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780031gk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780032cw- 64-pin plastic shrink dip (750 mils) mask rom m pd780032gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780032gk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780033cw- 64-pin plastic shrink dip (750 mils) mask rom m pd780033gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780033gk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780034cw- 64-pin plastic shrink dip (750 mils) mask rom m pd780034gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780034gk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780031cw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780031gc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780031gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780032cw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780032gc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780032gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780033cw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780033gc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780033gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780034cw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780034gc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780034gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd78f0034cw 64-pin plastic shrink dip (750 mils) flash memory m pd78f0034gc-ab8 64-pin plastic qfp (14 14 mm) flash memory m pd78f0034gk-8a8 64-pin plastic lqfp (12 12 mm) flash memory remark indicates rom code suffix.
35 chapter 1 outline ( m pd780024, 780034 subseries) 1.4 quality grade (1) m pd780024 subseries part number package quality grades m pd780021cw- 64-pin plastic shrink dip (750 mils) standard m pd780021gc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780021gk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780022cw- 64-pin plastic shrink dip (750 mils) standard m pd780022gc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780022gk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780023cw- 64-pin plastic shrink dip (750 mils) standard m pd780023gc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780023gk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780024cw- 64-pin plastic shrink dip (750 mils) standard m pd780024gc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780024gk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780021cw(a)- 64-pin plastic shrink dip (750 mils) special m pd780021gc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780021gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780022cw(a)- 64-pin plastic shrink dip (750 mils) special m pd780022gc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780022gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780023cw(a)- 64-pin plastic shrink dip (750 mils) special m pd780023gc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780023gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780024cw(a)- 64-pin plastic shrink dip (750 mils) special m pd780024gc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780024gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document number c11531e) published by nec corporation to know the specification of quality grades on the devices and its recommended applications.
36 chapter 1 outline ( m pd780024, 780034 subseries) (2) m pd780034 subseries part number package quality grades m pd780031cw- 64-pin plastic shrink dip (750 mils) standard m pd780031gc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780031gk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780032cw- 64-pin plastic shrink dip (750 mils) standard m pd780032gc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780032gk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780033cw- 64-pin plastic shrink dip (750 mils) standard m pd780033gc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780033gk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780034cw- 64-pin plastic shrink dip (750 mils) standard m pd780034gc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780034gk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780031cw(a)- 64-pin plastic shrink dip (750 mils) special m pd780031gc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780031gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780032cw(a)- 64-pin plastic shrink dip (750 mils) special m pd780032gc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780032gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780033cw(a)- 64-pin plastic shrink dip (750 mils) special m pd780033gc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780033gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780034cw(a)- 64-pin plastic shrink dip (750 mils) special m pd780034gc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780034gk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd78f0034cw 64-pin plastic shrink dip (750 mils) standard m pd78f0034gc-ab8 64-pin plastic qfp (14 14 mm) standard m pd78f0034gk-8a8 64-pin plastic lqfp (12 12 mm) standard remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document number c11531e) published by nec corporation to know the specification of quality grades on the devices and its recommended applications.
37 chapter 1 outline ( m pd780024, 780034 subseries) 1.5 pin configuration (top view) ? 64-pin plastic shrink dip (750 mils) m pd780021cw- , 780022cw- , 780023cw- , 780024cw- m pd780021cw(a)- , 780022cw(a)- , 780023cw(a)- , 780024cw(a)- m pd780031cw- , 780032cw- , 780033cw- , 780034cw- m pd780031cw(a)- , 780032cw(a)- , 780033cw(a)- , 780034cw(a)- m pd78f0034cw 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32 p33 p34/si31 p35/so31 p36/sck31 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic(v pp ) xt1 xt2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 cautions 1. connect directly ic (internally connected) pin to v ss0 or v ss1 . 2. connect av ss pin to v ss0 . remarks 1. when these devices are used in applications that require the reduction of noise generated from an on-chip microcontroller, the implementation of noise measures is recommended, such as supplying v dd0 and v dd1 independently, connecting v ss0 and v ss1 independently to ground lines, and so on. 2. pin connection in parentheses is intended for the m pd78f0034.
38 chapter 1 outline ( m pd780024, 780034 subseries) ? 64-pin plastic qfp (14 14 mm) m pd780021gc- -ab8, 780022gc- -ab8, 780023gc- -ab8, 780024gc- -ab8 m pd780021gc(a)- -ab8, 780022gc(a)- -ab8, 780023gc(a)- -ab8, 780024gc(a)- -ab8 m pd780031gc- -ab8, 780032gc- -ab8, 780033gc- -ab8, 780034gc- -ab8 m pd780031gc(a)- -ab8, 780032gc(a)- -ab8, 780033gc(a)- -ab8, 780034gc(a)- -ab8 m pd78f0034gc-ab8 ? 64-pin plastic lqfp (12 12 mm) m pd780021gk- -8a8, 780022gk- -8a8, 780023gk- -8a8, 780024gk- -8a8 m pd780021gk(a)- -8a8, 780022gk(a)- -8a8, 780023gk(a)- -8a8, 780024gk(a)- -8a8 m pd780031gk- -8a8, 780032gk- -8a8, 780033gk- -8a8, 780034gk- -8a8 m pd780031gk(a)- -8a8, 780032gk(a)- -8a8, 780033gk(a)- -8a8, 780034gk(a)- -8a8 m pd78f0034gk-8a8
39 chapter 1 outline ( m pd780024, 780034 subseries) cautions 1. connect directly ic (internally connected) pin to v ss0 or v ss1 . 2. connect av ss pin to v ss0 . remarks 1. when these devices are used in applications that require the reduction of noise generated from an on-chip microcontroller, the implementation of noise measures is recommended, such as supplying v dd0 and v dd1 independently, connecting v ss0 and v ss1 independently to ground lines, and so on. 2. pin connection in parentheses is intended for the m pd78f0034. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32 p33 p34/si31 p35/so31 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic (v pp ) xt1 xt2 reset av dd av ref p10/ani0 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p36/sck31 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1
40 chapter 1 outline ( m pd780024, 780034 subseries) a8 to a15 : address bus p70 to p75 : port7 ad0 to ad7 : address/data bus pcl : programmable clock adtrg : ad trigger input rd : read strobe ani0 to ani7 : analog input reset : reset asck0 : asynchronous serial clock rxd0 : receive data astb : address strobe sck30, sck31 : serial clock av dd : analog power supply si30, si31 : serial input av ref : analog reference voltage so30, so31 : serial output av ss : analog ground ti00, ti01, ti50, ti51 : timer input buz : buzzer clock to0, to50, to51 : timer output ic : internally connected txd0 : transmit data intp0 to intp3 : interrupt from peripherals v dd0 , v dd1 : power supply p00 to p03 : port0 v pp : programming power supply p10 to p17 : port1 v ss0 , v ss1 : ground p20 to p25 : port2 wait : wait p30 to p36 : port3 wr : write strobe p40 to p47 : port4 x1, x2 : crystal (main system clock) p50 to p57 : port5 xt1, xt2 : crystal (subsystem clock) p64 to p67 : port6
41 chapter 1 outline ( m pd780024, 780034 subseries) 1.6 78k/0 series expansion 78k/0 series expansion is shown below. the names in frames are subseries. note under planning pd780964 pd78098 80-pin the iebus controller was added to the pd78054 pd78044f 80-pin basic subseries for driving fip. display output total: 34 pd78014 pd780001 pd78002 pd78083 pd78002y pd780058 pd78058f pd78054 pd780034 pd780024 pd780024y pd78014h pd78018f pd78014y pd780208 pd780228 pd78044h pd780308 pd78064b pd78064 pd780308y pd78064y pd78098b 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42-/44-pin 100-pin 100-pin 80-pin 100-pin 100-pin 100-pin 80-pin iebus tm supported lcd drive fip tm drive 78k/0 series serial i/o of the pd78054 was enhanced. emi noise reduced version emi noise reduced version of the pd78054 uart and d/a converter were added to the pd78014 and i/o was enhanced an a/d converter of the pd780024 was enhanced serial i/o of the pd78018f was enhanced. emi noise reduced version of the pd78018f low-voltage (1.8 v) operation versions of the pd78014 with choice of several rom and ram capacities an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operation at a low voltage (1.8 v) the i/o and fip c/d of the pd78044f were enhanced. display output total: 53 the i/o and fip c/d of the pd78044h were enhanced. display output total: 48 n-ch open-drain i/o was added to the pd78044f. display output total: 34 pd780988 64-pin 64-pin inverter control the inverter control, timer, and sio of the pd780964 were enhanced. rom size and ram size were expanded pd780924 64-pin an a/d converter of the pd780924 was enhanced on-chip inverter control circuit and uart. emi noise reduced version sio of the pd78064 was enhanced. rom size and ram size were expanded emi noise reduced version of the pd78064 subseries for driving lcds. on-chip uart emi noise reduced version of the pd78098 on-chip controller/driver for driving automobile meters pd780973 80-pin meter control 100-pin pd78078 pd78070a pd78075b 100-pin 100-pin 100-pin control products in mass production products under development y subseries products are compatible with i 2 c bus. a timer was added to the pd78054 and the external interface function was enhanced emi noise reduced version of the pd78078 rom-less versions of the pd78078 serial i/o of the pd78078y was enhanced and only selected functions are provided pd78018fy pd780034y pd78054y pd78058fy pd780058y note pd78070ay pd78078y pd780018ay m m mm m mm m mm m m m m mm m mm m mm m mm mm m mm m m m mm m mm m m m m m m m m m m m m m m m m m m m m m m m m
42 chapter 1 outline ( m pd780024, 780034 subseries) major differences among those subseries are indicated below. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd external subseries capacity 8-bit 16-bit watch wdt a/d a/d d/a min. value extension control m pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v m pd78078 48 k to 60 k m pd78070a 61 2.7 v m pd780058 24 k to 60 k 2 ch 3 ch (time-division 68 1.8 v uart: 1 ch) m pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780034 8 k to 32 k 8 ch 3 ch (uart: 1 ch, time 51 1.8 v m pd780024 8 ch -division 3-wire: 1 ch) m pd78014h 2 ch 53 m pd78018f 8 k to 60 k m pd78014 8 k to 32 k 2.7 v m pd780001 8 k 1 ch 39 m pd78002 8 k to 16 k 1 ch 53 m pd78083 8 ch 1 ch (uart: 1 ch) 33 1.8 v inverter m pd780988 32 k to 60 k 3 ch note 1 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v control m pd780964 8 k to 32 k note 2 2 ch (uart: 2 ch) 2.7 v m pd780924 8 ch fip m pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive m pd780228 40 k to 60 k 3 ch 1 ch 72 4.5 v m pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 68 2.7 v m pd78044f 16 k to 40 k 2 ch lcd m pd780308 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 3 ch (time-division 57 2.0 v drive uart: 1 ch) m pd78064b 32 k 2 ch (uart: 1 ch) m pd78064 16 k to 32 k ieb us m pd78098b 40 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 69 2.7 v support m pd78098 32 k to 60 k meter m pd780973 24 k to 32 k 3 ch 1 ch 1 ch 1 ch 5 ch 2 ch (uart: 1 ch) 56 4.5 v control notes 1. 16-bit timer: 2 channels 10-bit timer: 1 channel 2. 10-bit timer: 1 channel
43 chapter 1 outline ( m pd780024, 780034 subseries) 1.7 block diagram 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer watch timer serial interface 30 serial interface 31 uart0 a/d converter interrupt control buzzer output clock output control ti00/to0/p70 ti01/p71 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 si31/p34 so31/p35 sck31/p36 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref buz/p75 pcl/p74 ani0/p10 - ani7/p17 intp0/p00 - intp3/p03 v dd0 v dd1 v ss0 v ss1 ic (v pp ) 78k/0 cpu core rom ram port 0 p00 - p03 port 1 p10 - p17 port 2 p20 - p25 port 3 p30 - p36 port 4 p40 - p47 port 5 p50 - p57 port 6 p64 - p67 port 7 p70 - p75 external access system control ad0/p40 - ad7/p47 a8/p50 - a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1 xt2 remarks 1. the internal rom and ram capacities depend on the product. 2. pin connection in parentheses is intended for the m pd78f0034.
44 chapter 1 outline ( m pd780024, 780034 subseries) 1.8 outline of function part number m pd780021 m pd780022 m pd780023 m pd780024 item m pd780031 m pd780032 m pd780033 m pd780034 m pd78f0034 internal memory rom 8 kbytes 16 kbytes 24 kbytes 32 kbytes 32 kbytes note (mask rom) (mask rom) (mask rom) (mask rom) (flash memory) high-speed ram 512 bytes 1024 bytes 1024 bytes note memory space 64 kbytes general register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction minimum instruction execution time changeable function execution time when main system 0.24 m s/0.48 m s/0.95 m s/1.91 m s/3.81 m s (@ 8.38-mhz operation) clock selected when subsystem 122 m s (@ 32.768-khz operation) clock selected instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits 8 bits) ? bit manipulate (set, reset, test, and boolean operation) ? bcd adjust, etc. i/o port total : 51 ? cmos input : 8 ? cmos i/o : 39 ? n-ch open-drain i/o 5-v breakdown : 4 a/d converter ? 8-bit resolution 8 channels ( m pd780021, 780022, 780023, 780024) ? 10-bit resolution 8 channels ( m pd780031, 780032, 780033, 780034, 78f0034) ? low-voltage operation: av dd = 2.7 to 5.5 v serial interface ? 3-wire serial i/o mode : 2 channels ? uart mode : 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel timer output three outputs: (8-bit pwm output enable: 2) clock output ? 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (8.38 mhz with main system clock) ? 32.768 khz (32.768 khz with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (8.38 mhz with main system clock) vectored interrupt maskable internal: 13, external: 5 non-maskable internal: 1 software 1 power supply voltage v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v operating ambient temperature t a = C40 to +85 c package ? 64-pin plastic shrink dip (750 mils) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register (ims).
45 chapter 1 outline ( m pd780024, 780034 subseries) 1.9 difference between standard grade and special grade standard grade : m pd780021, 780022, 780023, 780024 m pd780031, 780032, 780033, 780034, 78f0034 special grade : m pd780021(a), 780022(a), 780023(a), 780024(a) m pd780031(a), 780032(a), 780033(a), 780034(a) the standard and the special grade differ only in the quality level. 1.10 mask options the mask rom versions ( m pd780021, 780022, 780023, 780024, 780031, 780032, 780033, and 780034) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for device production. using the mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the m pd780024 and 780034 subseries are shown in table 1-1. table 1-1. mask options of mask rom versions pin names mask option p30 to p33 pull-up resistor connection can be specified in 1-bit units.
46 [memo]
47 chapter 2 outline ( m pd780024y, 780034y subseries) 2.1 features ? internal memory type program memory data memory part number (rom) (high-speed ram) m pd780021y, 780031y 8 kbytes 512 bytes m pd780022y, 780032y 16 kbytes m pd780023y, 780033y 24 kbytes 1024 bytes m pd780024y, 780034y 32 kbytes m pd78f0034y 32 kbytes note 1024 bytes note note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register. ? external memory expansion space: 64 kbytes ? minimum instruction execution time changeable from high speed (0.24 m s: @ 8.38-mhz operation with main system clock) to ultra-low speed (122 m s: @ 32.768-khz operation with subsystem clock) ? instruction set suited to system control ? bit manipulation possible in all address spaces ? multiply and divide instructions ? fifty-one i/o ports: (four n-ch open-drain ports) ? 8-bit resolution a/d converter : 8 channels ( m pd780024y subseries only) ? 10-bit resolution a/d converter : 8 channels ( m pd780034y subseries only) ? serial interface : 3 channels ?i 2 c mode : 1 channel ? 3-wire serial mode : 1 channel ? uart mode : 1 channel ? timer: five channels ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel ? vectored interrupts: 20 ? two types of on-chip clock oscillators (main system clock and subsystem clock) ? power supply voltage: v dd = 1.8 to 5.5 v (other than m pd78f0034y) v dd = 2.7 to 5.5 v ( m pd78f0034y only)
48 chapter 2 outline ( m pd780024y, 780034y subseries) 2.2 applications m pd780021y, 780022y, 780023y, 780024y m pd780031y, 780032y, 780033y, 780034y, 78f0034y av equipment, pagers, car audios, car electric equipment, office automation equipment, household electric appliances, etc. m pd780021y(a), 780022y(a), 780023y(a), 780024y(a) m pd780031y(a), 780032y(a), 780033y(a), 780034y(a) controllers of vending machines, gas detection breakers, safety devices, etc.
49 chapter 2 outline ( m pd780024y, 780034y subseries) 2.3 ordering information (1) m pd780024y subseries part number package internal rom m pd780021ycw- 64-pin plastic shrink dip (750 mils) mask rom m pd780021ygc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780021ygk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780022ycw- 64-pin plastic shrink dip (750 mils) mask rom m pd780022ygc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780022ygk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780023ycw- 64-pin plastic shrink dip (750 mils) mask rom m pd780023ygc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780023ygk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780024ycw- 64-pin plastic shrink dip (750 mils) mask rom m pd780024ygc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780024ygk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780021ycw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780021ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780021ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780022ycw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780022ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780022ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780023ycw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780023ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780023ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780024ycw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780024ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780024ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom remark indicates rom code suffix.
50 chapter 2 outline ( m pd780024y, 780034y subseries) (2) m pd780034y subseries part number package internal rom m pd780031ycw- 64-pin plastic shrink dip (750 mils) mask rom m pd780031ygc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780031ygk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780032ycw- 64-pin plastic shrink dip (750 mils) mask rom m pd780032ygc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780032ygk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780033ycw- 64-pin plastic shrink dip (750 mils) mask rom m pd780033ygc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780033ygk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780034ycw- 64-pin plastic shrink dip (750 mils) mask rom m pd780034ygc- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780034ygk- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780031ycw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780031ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780031ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780032ycw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780032ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780032ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780033ycw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780033ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780033ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd780034ycw(a)- 64-pin plastic shrink dip (750 mils) mask rom m pd780034ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) mask rom m pd780034ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) mask rom m pd78f0034ycw 64-pin plastic shrink dip (750 mils) flash memory m pd78f0034ygc-ab8 64-pin plastic qfp (14 14 mm) flash memory m pd78f0034ygk-8a8 64-pin plastic lqfp (12 12 mm) flash memory remark indicates rom code suffix.
51 chapter 2 outline ( m pd780024y, 780034y subseries) 2.4 quality grade (1) m pd780024y subseries part number package quality grades m pd780021ycw- 64-pin plastic shrink dip (750 mils) standard m pd780021ygc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780021ygk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780022ycw- 64-pin plastic shrink dip (750 mils) standard m pd780022ygc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780022ygk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780023ycw- 64-pin plastic shrink dip (750 mils) standard m pd780023ygc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780023ygk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780024ycw- 64-pin plastic shrink dip (750 mils) standard m pd780024ygc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780024ygk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780021ycw(a)- 64-pin plastic shrink dip (750 mils) special m pd780021ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780021ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780022ycw(a)- 64-pin plastic shrink dip (750 mils) special m pd780022ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780022ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780023ycw(a)- 64-pin plastic shrink dip (750 mils) special m pd780023ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780023ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780024ycw(a)- 64-pin plastic shrink dip (750 mils) special m pd780024ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780024ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document number c11531e) published by nec corporation to know the specification of quality grades on the devices and its recommended applications.
52 chapter 2 outline ( m pd780024y, 780034y subseries) (2) m pd780034y subseries part number package quality grades m pd780031ycw- 64-pin plastic shrink dip (750 mils) standard m pd780031ygc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780031ygk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780032ycw- 64-pin plastic shrink dip (750 mils) standard m pd780032ygc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780032ygk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780033ycw- 64-pin plastic shrink dip (750 mils) standard m pd780033ygc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780033ygk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780034ycw- 64-pin plastic shrink dip (750 mils) standard m pd780034ygc- -ab8 64-pin plastic qfp (14 14 mm) standard m pd780034ygk- -8a8 64-pin plastic lqfp (12 12 mm) standard m pd780031ycw(a)- 64-pin plastic shrink dip (750 mils) special m pd780031ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780031ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780032ycw(a)- 64-pin plastic shrink dip (750 mils) special m pd780032ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780032ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780033ycw(a)- 64-pin plastic shrink dip (750 mils) special m pd780033ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780033ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd780034ycw(a)- 64-pin plastic shrink dip (750 mils) special m pd780034ygc(a)- -ab8 64-pin plastic qfp (14 14 mm) special m pd780034ygk(a)- -8a8 64-pin plastic lqfp (12 12 mm) special m pd78f0034ycw 64-pin plastic shrink dip (750 mils) standard m pd78f0034ygc-ab8 64-pin plastic qfp (14 14 mm) standard m pd78f0034ygk-8a8 64-pin plastic lqfp (12 12 mm) standard remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document number c11531e) published by nec corporation to know the specification of quality grades on the devices and its recommended applications.
53 chapter 2 outline ( m pd780024y, 780034y subseries) 2.5 pin configuration (top view) ? 64-pin plastic shrink dip (750 mils) m pd780021ycw- , 780022ycw- , 780023ycw- , 780024ycw- m pd780021ycw(a)- , 780022ycw(a)- , 780023ycw(a)- , 780024ycw(a)- m pd780031ycw- , 780032ycw- , 780033ycw- , 780034ycw- m pd780031ycw(a)- , 780032ycw(a)- , 780033ycw(a)- , 780034ycw(a)- m pd78f0034ycw 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic (v pp ) xt1 xt2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 p33/scl0 p34 p35 p36 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 cautions 1. connect ic directly (internally connected) pin to v ss0 or v ss1 . 2. connect av ss pin to v ss0 . remarks 1. when these devices are used in applications that require the reduction of noise generated from an on-chip microcontroller, the implementation of noise measures is recommended, such as supplying v dd0 and v dd1 independently, connecting v ss0 and v ss1 independently to ground lines, and so on. 2. pin connection in parentheses is intended for the m pd78f0034.
54 chapter 2 outline ( m pd780024y, 780034y subseries) ? 64-pin plastic qfp (14 14 mm) m pd780021ygc- -ab8, 780022ygc- -ab8, 780023ygc- -ab8, 780024ygc- -ab8 m pd780021ygc(a)- -ab8, 780022ygc(a)- -ab8, 780023ygc(a)- -ab8, 780024ygc(a)- -ab8 m pd780031ygc- -ab8, 780032ygc- -ab8, 780033ygc- -ab8, 780034ygc- -ab8 m pd780031ygc(a)- -ab8, 780032ygc(a)- -ab8, 780033ygc(a)- -ab8, 780034ygc(a)- -ab8 m pd78f0034ygc-ab8 ? 64-pin plastic lqfp (12 12 mm) m pd780021ygk- -8a8, 780022ygk- -8a8, 780023ygk- -8a8, 780024ygk- -8a8 m pd780021ygk(a)- -8a8, 780022ygk(a)- -8a8, 780023ygk(a)- -8a8, 780024ygk(a)- -8a8 m pd780031ygk- -8a8, 780032ygk- -8a8, 780033ygk- -8a8, 780034ygk- -8a8 m pd780031ygk(a)- -8a8, 780032ygk(a)- -8a8, 780033ygk(a)- -8a8, 780034ygk(a)- -8a8 m pd78f0034ygk-8a8
55 chapter 2 outline ( m pd780024y, 780034y subseries) cautions 1. connect ic directly (internally connected) pin to v ss0 or v ss1 . 2. connect av ss pin to v ss0 . remarks 1. when these devices are used in applications that require the reduction of noise generated from an on-chip microcontroller, the implementation of noise measures is recommended, such as supplying v dd0 and v dd1 independently, connecting v ss0 and v ss1 independently to ground lines, and so on. 2. pin connection in parentheses is intended for the m pd78f0034. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 p33/scl0 p34 p35 p36 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic(v pp ) xt1 xt2 reset av dd av ref p10/ani0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50
56 chapter 2 outline ( m pd780024y, 780034y subseries) a8 to a15 : address bus pcl : programmable clock ad0 to ad7 : address/data bus rd : read strobe adtrg : ad trigger input reset : reset ani0 to ani7 : analog input rxd0 : receive data asck0 : asynchronous serial clock sck30 : serial clock astb : address strobe scl0 : serial clock av dd : analog power supply sda0 : serial data av ref : analog reference voltage si30 : serial input av ss : analog ground so30 : serial output buz : buzzer clock ti00, ti01, ti50, ti51 : timer input ic : internally connected to0, to50, to51 : timer output intp0 to intp3 : interrupt from peripherals txd0 : transmit data p00 to p03 : port 0 v dd0 , v dd1 : power supply p10 to p17 : port 1 v pp : programming power supply p20 to p25 : port 2 v ss0 , v ss1 : ground p30 to p36 : port 3 wait : wait p40 to p47 : port 4 wr : write strobe p50 to p57 : port 5 x1, x2 : crystal (main system clock) p64 to p67 : port 6 xt1, xt2 : crystal (subsystem clock) p70 to p75 : port 7
57 chapter 2 outline ( m pd780024y, 780034y subseries) 2.6 78k/0 series expansion 78k/0 series expansion is shown below. the names in frames are subseries. note under planning pd780964 pd78098 80-pin the iebus controller was added to the pd78054 pd78044f 80-pin basic subseries for driving fip. display output total: 34 pd78014 pd780001 pd78002 pd78083 pd78002y pd780058 pd78058f pd78054 pd780034 pd780024 pd780024y pd78014h pd78018f pd78014y pd780208 pd780228 pd78044h pd780308 pd78064b pd78064 pd780308y pd78064y pd78098b 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42-/44-pin 100-pin 100-pin 80-pin 100-pin 100-pin 100-pin 80-pin iebus tm supported lcd drive fip tm drive 78k/0 series serial i/o of the pd78054 was enhanced. emi noise reduced version emi noise reduced version of the pd78054 uart and d/a converter were added to the pd78014 and i/o was enhanced an a/d converter of the pd780024 was enhanced serial i/o of the pd78018f was enhanced. emi noise reduced version of the pd78018f low-voltage (1.8 v) operation versions of the pd78014 with choice of several rom and ram capacities an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operation at a low voltage (1.8 v) the i/o and fip c/d of the pd78044f were enhanced. display output total: 53 the i/o and fip c/d of the pd78044h were enhanced. display output total: 48 n-ch open-drain i/o was added to the pd78044f. display output total: 34 pd780988 64-pin 64-pin inverter control the inverter control, timer, and sio of the pd780964 were enhanced. rom size and ram size were expanded pd780924 64-pin an a/d converter of the pd780924 was enhanced on-chip inverter control circuit and uart. emi noise reduced version sio of the pd78064 was enhanced. rom size and ram size were expanded emi noise reduced version of the pd78064 subseries for driving lcds. on-chip uart emi noise reduced version of the pd78098 on-chip controller/driver for driving automobile meters pd780973 80-pin meter control 100-pin pd78078 pd78070a pd78075b 100-pin 100-pin 100-pin control products in mass production products under development y subseries products are compatible with i 2 c bus. a timer was added to the pd78054 and the external interface function was enhanced emi noise reduced version of the pd78078 rom-less versions of the pd78078 serial i/o of the pd78078y was enhanced and only selected functions are provided pd78018fy pd780034y pd78054y pd78058fy pd780058y note pd78070ay pd78078y pd780018ay m m mm m mm m mm m m m m mm m mm m mm m mm mm m mm m m m mm m mm m m m m m m m m m m m m m m m m m m m m m m m m
58 chapter 2 outline ( m pd780024y, 780034y subseries) the major differences among y subseries are indicated below. function rom capacity serial interface configuration i/o v dd subseries min. value control m pd78078y 48 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 88 1.8 v 3-wire with auto-transmit/receive : 1 ch m pd78070ay 3-wire/uart : 1 ch 61 2.7 v m pd780018ay 48 k to 60 k 3-wire with auto-transmit/receive : 1 ch 88 time-division 3-wire : 1 ch i 2 c bus (multimaster supported) : 1 ch m pd780058y 24 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 68 1.8 v 3-wire with auto-transmit/receive : 1 ch 3-wire/time-division uart : 1 ch m pd78058fy 48 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 69 2.7 v 3-wire with auto-transmit/receive : 1 ch m pd78054y 16 k to 60 k 3-wire/uart : 1 ch 2.0 v m pd780034y 8 k to 32 k uart : 1 ch 51 1.8 v 3-wire : 1 ch m pd780024y i 2 c bus (multimaster supported) : 1 ch m pd78018fy 8 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 53 2.7 v 3-wire with auto-transmit/receive : 1 ch m pd78014y 8 k to 32 k 3-wire/2-wire/sbi/i 2 c : 1 ch 3-wire with auto-transmit/receive : 1 ch m pd78002y 8 k to 16 k 3-wire/2-wire/sbi/i 2 c : 1 ch lcd drive m pd780308y 48 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 57 2.0 v 3-wire/time-division uart : 1 ch 3-wire : 1 ch m pd78064y 16 k to 32 k 3-wire/2-wire/i 2 c : 1 ch 3-wire/uart : 1 ch remark functions other than serial interface are the same as subseries without y.
59 chapter 2 outline ( m pd780024y, 780034y subseries) 2.7 block diagram ti00/to0/p70 16-bit timer/ event counter serial interface30 interrupt control buzzer output clock output control uart0 78k/0 cpu core port0 port1 port2 port3 port4 port5 port6 port7 p70 - p75 p64 - p67 p50 - p57 p40 - p47 p30 - p36 p20 - p25 p10 - p17 p00 - p03 external access system control reset x1 x2 xt1 xt2 rd/p64 wr/p65 wait/p66 astb/p67 ad0/p40 - ad7/p47 a8/p50 - a15/p57 rom ram a/d converter i 2 c bus v dd0 v dd1 v ss0 v ss1 ic (v pp ) watchdog timer watch timer 8-bit timer/ event counter50 8-bit timer/ event counter51 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref sda0/p32 scl0/p33 buz/p75 pcl/p74 ani0/p10 - ani7/p17 intp0/p00 - intp3/p03 ti01/p71 remarks 1. the internal rom and ram capacities depend on the product. 2. pin connection in parentheses is intended for the m pd78f0034y.
60 chapter 2 outline ( m pd780024y, 780034y subseries) 2.8 outline of function part number m pd780021y m pd780022y m pd780023y m pd780024y item m pd780031y m pd780032y m pd780033y m pd780034y m pd78f0034y internal memory rom 8 kbytes 16 kbytes 24 kbytes 32 kbytes 32 kbytes note (mask rom) (mask rom) (mask rom) (mask rom) (flash memory) high-speed ram 512 bytes 1024 bytes 1024 bytes note memory space 64 kbytes general register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction minimum instruction execution time changeable function execution time when main system 0.24 m s/0.48 m s/0.95 m s/1.91 m s/3.81 m s (@ 8.38-mhz operation) clock selected when subsystem 122 m s (@ 32.768-khz operation) clock selected instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits 8 bits) ? bit manipulate (set, reset, test, and boolean operation) ? bcd adjust, etc. i/o port total : 51 ? cmos input : 8 ? cmos i/o : 39 ? n-ch open-drain i/o 5-v breakdown : 4 a/d converter ? 8-bit resolution 8 channels ( m pd780021y, 780022y, 780023y, 780024y) ? 10-bit resolution 8 channels ( m pd780031y, 780032y, 780033y, 780034y, 78f0034y) ? low-voltage operation: av dd = 2.7 to 5.5 v serial interface ? 3-wire serial i/o mode : 1 channel ? uart mode : 1 channel ? i 2 c bus mode : 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel timer output three outputs: (8-bit pwm output enable: 2) clock output ? 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (8.38 mhz with main system clock) ? 32.768 khz (32.768 khz with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (8.38 mhz with main system clock) vectored interrupt maskable interrupt internal: 13, external: 5 non-maskable interrupt internal: 1 software interrupt 1 power supply voltage v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v operating ambient temperature t a = C40 to +85 c package ? 64-pin plastic shrink dip (750 mils) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register (ims).
61 chapter 2 outline ( m pd780024y, 780034y subseries) 2.9 difference between standard grade and special grade standard grade : m pd780021y, 780022y, 780023y, 780024y m pd780031y, 780032y, 780033y, 780034y, 78f0034y special grade : m pd780021y(a), 780022y(a), 780023y(a), 780024y(a) m pd780031y(a), 780032y(a), 780033y(a), 780034y(a) the standard and the special grade differ only in the quality level. 2.10 mask options the mask rom versions ( m pd780021y, 780022y, 780023y, 780024y, 780031y, 780032y, 780033y, 780034y) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for device production. using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the m pd780024y, 780034y subseries are shown in table 2-1. table 2-1. mask options of mask rom versions pin names mask option p30, p31 pull-up resistor connection can be specified in 1-bit units.
62 [memo]
63 pin name input/output function after reset alternate function p00 input/output input intp0 p01 intp1 p02 intp2 p03 intp3/adtrg p10 to p17 input port 1 input ani0 to ani7 8-bit input only port. p20 input/output input si30 p21 so30 p22 sck30 p23 rxd0 p24 txd0 p25 asck0 p30 input/output input p31 p32 p33 p34 si31 p35 so31 p36 sck31 p40 to p47 input/output port 4 input ad0 to ad7 8-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 input/output port 5 input a8 to a15 8-bit input/output port leds can be driven directly. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. p64 input/output input rd p65 wr p66 wait p67 astb chapter 3 pin function ( m pd780024, 780034 subseries) 3.1 pin function list (1) port pins (1/2) port 0 4-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 2 6-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 3 7-bit input/output port input/output mode can be specified bit-wise. n-ch open-drain input/output port on-chip pull-up resistor can be specified by mask option. (mask rom version only) leds can be driven directly. if used as an input port, an on-chip pull-up resistor can be used by software. port 6 4-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software.
64 chapter 3 pin function ( m pd780024, 780034 subseries) pin name input/output function after reset alternate function intp0 input input p00 intp1 p01 intp2 p02 intp3 p03/adtrg si30 input serial interface serial data input input p20 si31 p34 so30 output serial interface serial data output input p21 so31 p35 sck30 input/output serial interface serial clock input/output input p22 sck31 p36 rxd0 input asynchronous serial interface serial data input input p23 txd0 output asynchronous serial interface serial data output input p24 asck0 input asynchronous serial interface serial clock input input p25 ti00 input external count clock input to 16-bit timer (tm0) input p70/to0 capture trigger input to tm0 capture register (cr01) ti01 capture trigger input to tm0 capture register (cr00) p71 ti50 external count clock input to 8-bit timer (tm50) p72/to50 ti51 external count clock input to 8-bit timer (tm51) p73/to51 to0 output 16-bit timer tm0 output input p70/ti00 to50 8-bit timer (tm50) output (also used for 8-bit pwm output) input p72/ti50 to51 8-bit timer (tm51) output (also used for 8-bit pwm output) p73/ti51 pcl output clock output (for main system clock and subsystem clock input p74 trimming) buz output buzzer output input p75 ad0 to ad7 input/output lower-order address/data bus when expanding external memory input p40 to p47 a8 to a15 output high-order address bus when expanding external memory input p50 to p57 rd output strobe signal output for read operation from external memory input p64 wr strobe signal output for write operation from external memory p65 pin name input/output function after reset alternate function p70 input/output input ti00/to0 p71 ti01 p72 ti50/to50 p73 ti51/to51 p74 pcl p75 buz (2) non-port pins (1/2) (1) port pins (2/2) external interrupt request input with specifiable valid edges (rising edge, falling edge, both rising and falling edges) port 7 6-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software.
65 chapter 3 pin function ( m pd780024, 780034 subseries) (2) non-port pins (2/2) pin name input/output function after reset alternate function wait input wait insertion when accessing external memory input p66 astb output strobe output externally latching address information input p67 output to ports 4, 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input av dd a/d converter analog power supply. connect to v dd0 or v dd1 av ss a/d converter ground potential. connect to v ss0 or v ss1 reset input system reset input x1 input crystal connection for main system clock oscillation x2 xt1 input crystal connection for subsystem clock oscillation xt2 v dd0 positive power supply v ss0 ground potential v dd1 positive power supply other than port v ss1 ground potential other than port ic internally connected. connect directly to v ss0 or v ss1 v pp high-voltage application for program write/verify connect directly to v ss0 or v ss1 in normal operating mode.
66 chapter 3 pin function ( m pd780024, 780034 subseries) 3.2 description of pin functions 3.2.1 p00 to p03 (port 0) these are 4-bit input/output ports. besides serving as input/output ports, they function as an external interrupt input, and a/d converter external trigger input. the following operating modes can be specified bit-wise. (1) port mode these ports function as 4-bits input/output ports. p00 to p03 can be specified for input or output ports bit-wise with a port mode register 0 (pm0). when they are used as input ports, on-chip pull-up resistors can be used for them by defining the pull-up resistor option register 0 (pu0). (2) control mode in this mode, these ports function as an external interrupt request input, and a/d converter external trigger input. (a) intp0 to intp3 intp0 to intp3 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). (b) adtrg a/d converter external trigger input. caution when p03 is used as an a/d converter external trigger input, specify the valid edge by bits 1, 2 (ega00, ega01) of a/d converter mode register (adm0) and set interrupt mask flag (pmk3) to 1. 3.2.2 p10 to p17 (port 1) these are 8-bit input only ports. besides serving as input ports, they function as an a/d converter analog input. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input only ports. (2) control mode these ports function as a/d converter analog input pins (ani0 to ani7).
67 chapter 3 pin function ( m pd780024, 780034 subseries) 3.2.3 p20 to p25 (port 2) these are 6-bit input/output ports. besides serving as input/output ports, they function as data input/output to/from the serial interface and clock input/output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 6-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 2 (pm2). when they are used as input ports, on-chip pull-up resistors can be used for them by setting pull-up resistor option register 2 (pu2). (2) control mode these ports function as serial interface data input/output and clock input/output functions. (a) si30 and so30 serial interface serial data input/output pins. (b) sck30 serial interface serial clock input/output pin. (c) r x d0, t x d0 asynchronous serial interface serial data input/output pins. (d) asck0 asynchronous serial interface serial clock input pin. 3.2.4 p30 to p36 (port 3) these are 7-bit input/output ports. beside serving as input/output ports, they function as serial interface data input/output and clock input/output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 7-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 3 (pm3). p30 to p33 are n-ch open drain input/output port. on-chip pull-up resistor can be used by mask option. (mask rom version only) when p34 to p36 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register 3 (pu3). (2) control mode these ports function as serial interface data input/output and clock input/output. (a) si31 and so31 serial interface serial data input/output pins. (b) sck31 serial interface serial clock input/output pin.
68 chapter 3 pin function ( m pd780024, 780034 subseries) 3.2.5 p40 to p47 (port 4) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address/data bus. the interrupt request flag (krif) can be set to 1 by detecting a falling edge. the following operating mode can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified in 1-bit units for input or output ports by using port mode register 4 (pm4). when they are used as input ports, on-chip pull-up resistors can be used by setting pull-up resistor option register 4 (pu4). (2) control mode these ports function as low-order address/data bus pins (ad0 to ad7) in external memory expansion mode. when pins are used as an address/data bus, the pull-up resistor is automatically disabled. 3.2.6 p50 to p57 (port 5) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address bus. port 5 can drive leds directly. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 5 (pm5). when they are used as input ports, on-chip pull-up resistors can be used by setting pull- up resistor option register 5 (pu5). (2) control mode these ports function as high-order address bus pins (a8 to a15) in external memory expansion mode. when pins are used as an address bus, the pull-up resistor is automatically disabled. 3.2.7 p64 to p67 (port 6) these are 4-bit input/output ports. besides serving as input/output ports, they are used for control in external memory expansion mode. the following operating modes can be specified bit-wise. (1) port mode these ports function as 4-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 6 (pm6). when they are used as input ports, on-chip pull-up resistors can be used by setting pull-up resistor option register 6 (pu6). (2) control mode these ports function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. when a pin is used as a control signal output, the pull-up resistor is automatically disabled. caution when external wait is not used in external memory expansion mode, p66 can be used as an input/output port.
69 chapter 3 pin function ( m pd780024, 780034 subseries) 3.2.8 p70 to p75 (port 7) these are 6-bit input/output ports. besides serving as input/output ports, they function as a timer input/output, clock output, and buzzer output. the following operating modes can be specified bit-wise. (1) port mode port 7 functions as a 6-bit input/output port. bit-wise specification as an input port or output port is possible by means of port mode register 7 (pm7). when used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register 7 (pu7). p70 and p71 are also 16-bit timer/event counter capture trigger signal input pins with a valid edge input. (2) control mode port 7 functions as timer input/output, clock output and buzzer output. (a) ti00 external count clock input pin to 16-bit timer/event counter and capture trigger signal input pin to 16-bit timer/ event counter capture register (cr01). (b) ti01 capture trigger signal input pin to 16-bit timer/event counter capture register (cr00). (c) ti50 and ti51 8-bit timer/event counter external count clock input pins. (d) to0, to50, and to51 timer output pins. (e) pcl clock output pin. (f) buz buzzer output pin. 3.2.9 av ref this is an a/d converter reference voltage input pin. when no a/d converter is used, connect this pin to v ss0 . 3.2.10 av dd this is an analog power supply pin of a/d converter. always use the same voltage as that of the v dd0 pin even when no a/d converter is used. 3.2.11 av ss this is a ground voltage pin of a/d converter. always use the same voltage as that of the v ss0 pin even when no a/d converter is used.
70 chapter 3 pin function ( m pd780024, 780034 subseries) 3.2.12 reset this is a low-level active system reset input pin. 3.2.13 x1 and x2 crystal resonator connect pins for main system clock oscillation. for external clock supply, input clock signal to x1 and its inverted signal to x2. 3.2.14 xt1 and xt2 crystal resonator connect pins for subsystem clock oscillation. for external clock supply, input the clock signal to xt1 and its inverted signal to xt2. 3.2.15 v dd0 and v dd1 v dd0 is a positive power supply port pin. v dd1 is a positive power supply pin other than port pin. 3.2.16 v ss0 and v ss1 v ss0 is a ground potential port pin. v ss1 is a ground potential pin other than port pin. 3.2.17 v pp (flash memory versions only) high-voltage apply pin for flash memory programming mode setting and program write/verify. connect directly to v ss0 or v ss1 in the normal operating mode. 3.2.18 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the m pd780024, 780034 subseries at delivery. connect it directly to the v ss0 or v ss1 with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss0 pin or v ss1 pin, because the wiring between those two pins is too long or an external noise is input to the ic pin, the user's program may not operate normally. ? connect ic pins to v ss0 pins or v ss1 pins directly. as short as possible ic v ss0 or v ss1
71 chapter 3 pin function ( m pd780024, 780034 subseries) 3.3 pin input/output circuits and recommended connection of unused pins table 3-1 shows the types of pin input/output circuit and the recommended connections of unused pins. refer to figure 3-1 for the configuration of the input/output circuit of each type. table 3-1. pin input/output circuit types (1/2) pin name input/output circuit type input/output recommended connection of unused pins p00/intp0 8-c input/output independently connect to v ss0 via a resistor. p01/intp1 p02/intp2 p03/intp3 p10/ani0 to p17/ani7 25 input independently connect to v dd0 or v ss0 via a resistor. p20/si30 8-c input/output p21/so30 5-h p22/sck30 8-c p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q input/output independently connect to v dd0 via a resistor. (for mask rom version) p30, p31 13-p (for flash memory version) p32, p33 13-s (for mask rom version) p32, p33 13-r (for flash memory version) p34/si31 8-c independently connect to v dd0 or v ss0 via a resistor. p35/so31 5-h p36/sck31 8-c p40/ad0 to p47/ad7 5-h input/output independently connect to v dd0 via a resistor.
72 chapter 3 pin function ( m pd780024, 780034 subseries) table 3-1. pin input/output circuit types (2/2) pin name input/output circuit type input/output recommended connection of unused pins p50/a8 to p57/a15 5-h input/output independently connect to v dd0 or v ss0 via a resistor. p64/rd input/output p65/wr p66/wait p67/astb p70/ti00/to0 8-c p71/ti01 p72/ti50/to50 p73/ti51/to51 p74/pcl 5-h p75/buz reset 2 input xt1 16 connect to v dd0 . xt2 leave open. av dd connect to v dd0 . av ref connect to v ss0 . av ss ic (for mask rom version) connect directly to v ss0 or v ss1 . v pp (for flash memory version)
73 chapter 3 pin function ( m pd780024, 780034 subseries) figure 3-1 pin input/output circuit of list (1/2) type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pullup enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pullup enable type 13-q data output disable in/out n-ch v dd0 mask option data output disable in/out n-ch data output disable in/out n-ch type 13-p input enable v ss0 input enable v ss0 type 13-r v ss0 v ss0 v ss0
74 chapter 3 pin function ( m pd780024, 780034 subseries) figure 3-1 pin input/output circuit of list (2/2) p-ch feedback cut-off xt1 xt2 type 13-s type 16 data output disable in/out n-ch input enable comparator + p-ch n-ch v ref (threshold voltage) v ss0 type 25 v ss0 in v dd0 mask option
75 chapter 4 pin function ( m pd780024y, 780034y subseries) 4.1 pin function list (1) port pins (1/2) pin name input/output function after reset alternate function p00 input/output input intp0 p01 intp1 p02 intp2 p03 intp3/adtrg p10 to p17 input port 1 input ani0 to ani7 8-bit input only port. p20 input/output input si30 p21 so30 p22 sck30 p23 rxd0 p24 txd0 p25 asck0 p30 input/output input p31 p32 sda0 p33 scl0 p34 p35 p36 p40 to p47 input/output port 4 input ad0 to ad7 8-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 input/output port 5 input a8 to a15 8-bit input/output port leds can be driven directly. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. p64 input/output input rd p65 wr p66 wait p67 astb port 0 4-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 2 6-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 3 7-bit input/output port input/output mode can be specified bit-wise. n-ch open-drain input/output port on-chip pull-up resistor can be specified by mask option. (p30 and p31 are mask rom version only.) leds can be driven directly. if used as an input port, an on-chip pull-up resistor can be used by software. port 6 4-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software.
76 chapter 4 pin function ( m pd780024y, 780034y subseries) (1) port pins (2/2) (2) non-port pins (1/2) pin name input/output function after reset alternate function p70 input/output input ti00/to0 p71 ti01 p72 ti50/to50 p73 ti51/to51 p74 pcl p75 buz port 7 6-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. pin name input/output function after reset alternate function intp0 input input p00 intp1 p01 intp2 p02 intp3 p03/adtrg si30 input serial interface serial data input input p20 so30 output serial interface serial data output input p21 sda0 input/output serial interface serial data input/output input p32 sck30 input/output serial interface serial clock input/output input p22 scl0 p33 rxd0 input asynchronous serial interface serial data input input p23 txd0 output asynchronous serial interface serial data output input p24 asck0 input asynchronous serial interface serial clock input input p25 ti00 input external count clock input to 16-bit timer (tm0) input p70/to0 capture trigger input to tm0 capture register (cr01) ti01 capture trigger input to tm0 capture register (cr00) p71 ti50 external count clock input to 8-bit timer (tm50) p72/to50 ti51 external count clock input to 8-bit timer (tm51) p73/to51 to0 output 16-bit timer tm0 output input p70/ti00 to50 8-bit timer (tm50) output (also used for 8-bit pwm output) input p72/ti50 to51 8-bit timer (tm51) output (also used for 8-bit pwm output) p73/ti51 pcl output clock output (for main system clock and subsystem clock input p74 trimming) buz output buzzer output input p75 ad0 to ad7 input/output lower-order address/data bus when expanding external memory input p40 to p47 a8 to a15 output high-order address bus when expanding external memory input p50 to p57 rd output strobe signal output for read operation from external memory input p64 wr strobe signal output for write operation from external memory p65 wait input wait insertion when accessing external memory input p66 astb output strobe output externally latching address information input p67 output to ports 4, 5 to access external memory external interrupt request input with specifiable valid edges (rising edge, falling edge, both rising and falling edges)
77 chapter 4 pin function ( m pd780024y, 780034y subseries) (2) non-port pins (2/2) pin name input/output function after reset alternate function ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input av dd a/d converter analog power supply. connect to v dd0 or v dd1 av ss a/d converter ground potential. connect to v ss0 or v ss1 reset input system reset input x1 input crystal connection for main system clock oscillation x2 xt1 input crystal connection for subsystem clock oscillation xt2 v dd0 positive power supply v ss0 ground potential v dd1 positive power supply other than port v ss1 ground potential other than port ic internally connected. connect directly to v ss0 or v ss1 v pp high-voltage application for program write/verify connect directly to v ss0 or v ss1 in normal operating mode.
78 chapter 4 pin function ( m pd780024y, 780034y subseries) 4.2 description of pin functions 4.2.1 p00 to p03 (port 0) these are 4-bit input/output ports. besides serving as input/output ports, they function as an external interrupt input, and a/d converter external trigger input pins. the following operating modes can be specified bit-wise. (1) port mode in this mode, these ports function as 4-bit input/output ports. p00 to p03 can be specified for input or output ports bit-wise with a port mode register 0 (pm0). when they are used as input ports, on-chip pull-up resistors can be used for them by setting pull-up resistor option register 0 (pu0). (2) control mode in this mode, these ports function as an external interrupt request input, and a/d converter external trigger input pins. (a) intp0 to intp3 intp0 to intp3 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). (b) adtrg a/d converter external trigger input pin. caution when p03 is used as an a/d converter external trigger input, specify the valid edge by bits 1, 2 (ega00, ega01) of a/d converter mode register (adm0) and set interrupt mask flag (pmk3) to 1. 4.2.2 p10 to p17 (port 1) these are 8-bit input only ports. besides serving as input ports, they function as an a/d converter analog input. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input only ports. (2) control mode these ports function as a/d converter analog input pins (ani0 to ani7).
79 chapter 4 pin function ( m pd780024y, 780034y subseries) 4.2.3 p20 to p25 (port 2) these are 6-bit input/output ports. besides serving as input/output ports, they function as data input/output to/from the serial interface and clock input/output functions. the following operating modes can be specified bit-wise. (1) port mode these ports function as 6-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 2 (pm2). when they are used as input ports, on-chip pull-up resistors can be used for them by setting pull-up resistor option register 2 (pu2). (2) control mode these ports function as serial interface data input/output and clock input/output. (a) si30 and so30 serial interface serial data input/output pins. (b) sck30 serial interface serial clock input/output pin. (c) r x d0, t x d0 asynchronous serial interface serial data input/output pins. (d) asck0 asynchronous serial interface serial clock input pin. 4.2.4 p30 to p36 (port 3) these are 7-bit input/output ports. beside serving as input/output ports, they function as serial interface data input/ output and clock input/output. p30 to p33 (port 3) can drive leds directly. the following operating modes can be specified bit-wise. (1) port mode these ports function as 7-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 3 (pm3). p30 to p33 are n-ch open drain output. mask rom version can contain pull-up resistors in p30 and p31 with the mask option. when p34 to p36 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register 3 (pu3). (2) control mode these ports function as serial interface serial data input/output and clock input/output. (a) sda0 serial interface serial data input/output pin. (b) scl0 serial interface serial clock input/output pin.
80 chapter 4 pin function ( m pd780024y, 780034y subseries) 4.2.5 p40 to p47 (port 4) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address/data bus. the interrupt request flag (krif) can be set to 1 by detecting a falling edge. the following operating mode can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise for input or output ports by using the port mode register 4 (pm4). when they are used as input ports, on-chip pull-up resistors can be used by setting pull-up resistor option register 4 (pu4). (2) control mode these ports function as low-order address/data bus pins (ad0 to ad7) in external memory expansion mode. when pins are used as an address/data bus, the pull-up resistor is automatically disabled. 4.2.6 p50 to p57 (port 5) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address bus. port 5 can drive leds directly. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 5 (pm5). when they are used as input ports, on-chip pull-up resistors can be used by setting pull- up resistor option register 5 (pu5). (2) control mode these ports function as high-order address bus pins (a8 to a15) in external memory expansion mode. when pins are used as an address bus, the pull-up resistor is automatically disabled. 4.2.7 p64 to p67 (port 6) these are 4-bit input/output ports. besides serving as input/output ports, they are used for control in external memory expansion mode. the following operating modes can be specified bit-wise. (1) port mode these ports function as 4-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 6 (pm6). when they are used as input ports, on-chip pull-up resistors can be used by setting pull-up resistor option register 6 (pu6). (2) control mode these ports function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. when a pin is used as a control signal output, the pull-up resistor is automatically disabled. caution when external wait is not used in external memory expansion mode, p66 can be used as an input/output port.
81 chapter 4 pin function ( m pd780024y, 780034y subseries) 4.2.8 p70 to p75 (port 7) these are 6-bit input/output ports. besides serving as input/output ports, they function as a timer input/output, clock output, and buzzer output. the following operating modes can be specified bit-wise. (1) port mode port 7 functions as a 6-bit input/output port. bit-wise specification as an input port or output port is possible by means of port mode register 7 (pm7). when used as input ports, on-chip pull-up resistors can be used by setting pull-up resistor option register 7 (pu7). p70 and p71 also become a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. (2) control mode port 7 functions as timer input/output, clock output and buzzer output. (a) ti00 pin for external count clock input to the 16-bit timer/event counter and pin for capture trigger signal input to the 16-bit timer/event counter capture register (cr01). (b) ti01 pin for capture trigger signal input to the 16-bit timer/event counter capture resister (cr00). (c) ti50, ti51 pin for external count clock input to the 8-bit timer/event counter. (d) to0, to50, to51 timer output pin. (e) pcl clock output pin. (f) buz buzzer output pin. 4.2.9 av ref this is an a/d converter reference voltage input pin. when no a/d converter is used, connect this pin to v ss0 . 4.2.10 av dd this is an analog power supply pin of a/d converter. always use the same voltage as that of the v dd0 pin even when no a/d converter is used. 4.2.11 av ss this is a ground voltage pin of a/d converter. always use the same voltage as that of the v ss0 pin even when no a/d converter is used.
82 chapter 4 pin function ( m pd780024y, 780034y subseries) 4.2.12 reset this is a low-level active system reset input pin. 4.2.13 x1 and x2 crystal resonator connect pins for main system clock oscillation. for external clock supply, input the clock signal to x1 and its inverted signal to x2. 4.2.14 xt1 and xt2 crystal resonator connect pins for subsystem clock oscillation. for external clock supply, input the clock signal to xt1 and its inverted signal to xt2. 4.2.15 v dd0 , v dd1 v dd0 is a positive power supply pin. v dd1 is a positive power supply pin other than port pin. 4.2.16 v ss0 , v ss1 v ss0 is a ground potential port pin. v ss1 is a ground potential pin other than port pin. 4.2.17 v pp (flash memory versions only) high-voltage apply pin for flash memory programming mode setting and program write/verify. connect directly to v ss0 or v ss1 in normal operating mode. 4.2.18 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the m pd780024, 780034y subseries at delivery. connect it directly to the v ss0 or v ss1 with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss0 pin or v ss1 pin, because the wiring between those two pins is too long or an external noise is input to the ic pin, the user's program may not operate normally. ? connect ic pins to v ss0 pins or v ss1 pins directly. as short as possible ic v ss0 or v ss1
83 chapter 4 pin function ( m pd780024y, 780034y subseries) 4.3 pin input/output circuits and recommended connection of unused pins table 4-1 shows the types of pin input/output circuit and the recommended connections of unused pins. refer to figure 4-1 for the configuration of the input/output circuit of each type. table 4-1. pin input/output circuit types (1/2) pin name input/output circuit type input/output recommended connection of unused pins p00/intp0 8-c input/output independently connect to v ss0 via a resistor. p01/intp1 p02/intp2 p03/intp3 p10/ani0 to p17/ani7 25 input independently connect to v dd0 or v ss0 via a resistor. p20/si30 8-c input/output p21/so30 5-h p22/sck30 8-c p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q input/output independently connect to v ss0 via a resistor. (for mask rom version) p30, p31 13-p (for flash memory version) p32/sda0 13-r p33/scl0 p34 8-c independently connect to v dd0 or v ss0 via a resistor. p35 5-h p36 8-c p40/ad0 to p47/ad7 5-h input/output independently connect to v ss0 via a resistor.
84 chapter 4 pin function ( m pd780024y, 780034y subseries) table 4-1. pin input/output circuit types (2/2) pin name input/output circuit type input/output recommended connection of unused pins p50/a8 to p57/a15 5-h input/output independently connect to v dd0 or v ss0 via a resistor. p64/rd input/output p65/wr p66/wait p67/astb p70/ti00/to0 8-c p71/ti01 p72/ti50/to50 p73/ti51/to51 p74/pcl 5-h p75/buz reset 2 input xt1 16 connect to v dd0 xt2 leave open. av dd connect to v dd0 av ref connect to v ss0 av ss ic (for mask rom version) v pp connect directly to v ss0 or v ss1 (for flash memory version)
85 chapter 4 pin function ( m pd780024y, 780034y subseries) figure 4-1 pin input/output circuit of list (1/2) type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pullup enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pullup enable type 13-q data output disable in/out n-ch v dd0 mask option data output disable in/out n-ch data output disable in/out n-ch type 13-p input enable v ss0 input enable v ss0 type 13-r v ss0 v ss0 v ss0
86 chapter 4 pin function ( m pd780024y, 780034y subseries) figure 4-1 pin input/output circuit of list (2/2) p-ch feedback cut-off xt1 xt2 type 16 input enable comparator + p-ch n-ch v ref (threshold voltage) type 25 v ss0 in
87 chapter 5 cpu architecture 5.1 memory spaces m pd780024, 780034, 780024y, 780034y subseries can access 64-kbyte memory space respectively. figures 5-1 to 5-5 show memory maps. caution in case of the internal memory capacity, the initial value of memory size switching register (ims) of all products ( m pd780024, 780034, 780024y, and 780034y subseries) is fixed (cfh). therefore, set the value corresponding to each products indicated below. m pd780021, 780031, 780021y, 780031y : 42h m pd780022, 780032, 780022y, 780032y : 44h m pd780023, 780033, 780023y, 780033y : c6h m pd780024, 780034, 780024y, 780034y : c8h m pd78f0034, 78f0034y : value for mask rom version figure 5-1. memory map ( m pd780021, 780031, 780021y, 780031y) 0000h data memory space general registers 32 8 bits internal rom 8192 8 bits 1fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 55296 8 bits program memory space 2000h 1fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits special function registers (sfrs) 256 8 bits reserved fd00h fcffh
88 chapter 5 cpu architecture figure 5-2. memory map ( m pd780022, 780032, 780022y, 780032y) 0000h data memory space general registers 32 8 bits internal rom 16384 8 bits 3fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 47104 8 bits program memory space 4000h 3fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits special function registers (sfrs) 256 8 bits reserved fd00h fcffh
89 chapter 5 cpu architecture figure 5-3. memory map ( m pd780023, 780033, 780023y, 780033y) 0000h data memory space general registers 32 8 bits internal rom 24576 8 bits 5fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 38912 8 bits program memory space 6000h 5fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh
90 chapter 5 cpu architecture figure 5-4. memory map ( m pd780024, 780034, 780024y, 780034y) 0000h data memory space internal rom 32768 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 30720 8 bits program memory space 8000h 7fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh general registers 32 8 bits
91 chapter 5 cpu architecture figure 5-5. memory map ( m pd78f0034, 78f0034y) 0000h data memory space general registers 32 8 bits internal flash memory 32768 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 30720 8 bits program memory space 8000h 7fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh
92 chapter 5 cpu architecture 5.1.1 internal program memory space the internal program memory space contains the program and table data. normally, it is addressed with the program counter (pc). the m pd780024, 780034, 780024y, and 780034y subseries products incorporate an on-chip rom (or flash memory), as listed below. table 5-1. internal rom capacity part number internal rom type capacity m pd780021, 780031, 780021y, 780031y mask rom 8192 8 bits (0000h to 1fffh) m pd780022, 780032, 780022y, 780032y 16384 8 bits (0000h to 3fffh) m pd780023, 780033, 780023y, 780033y 24576 8 bits (0000h to 5fffh) m pd780024, 780034, 780024y, 780034y 32768 8 bits (0000h to 7fffh) m pd78f0034, 78f0034y flash memory 32768 8 bits (0000h to 7fffh) the internal program memory space is divided into the following three areas.
93 chapter 5 cpu architecture (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16- bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses. table 5-2. vector table vector table address interrupt source 0000h reset input 0004h intwdt 0006h intp0 0008h intp1 000ah intp2 000ch intp3 000eh intser0 0010h intsr0 0012h intst0 0014h intcsi30 0016h intcsi31 note 1 0018h intiic0 note 2 001ah intwti 001ch inttm00 001eh inttm01 0020h inttm50 0022h inttm51 0024h intad0 0026h intwt 0028h intkr 003eh brk notes 1. m pd780024, 780034 subseries only 2. m pd780024y, 780034y subseries only (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf).
94 chapter 5 cpu architecture 5.1.2 internal data memory space the m pd780024, 780034, 780024y, and 780034y subseries products incorporate an on-chip high-speed ram, as listed below. table 5-3. internal high-speed ram capacity product internal high-speed ram m pd780021, 780031, 780021y, 780031y 512 8 bits (fd00h to feffh) m pd780022, 780032, 780022y, 780032y m pd780023, 780033, 780023y, 780033y 1024 8 bits (fb00h to feffh) m pd780024, 780034, 780024y, 780034y m pd78f0034, 78f0034y the 32-byte area fee0h to feffh is allocated four general-purpose register banks composed of eight 8-bit registers. the internal high-speed ram can also be used as a stack memory. 5.1.3 special function register (sfr) area an on-chip peripheral hardware special-function register (sfr) is allocated in the area ff00h to ffffh. (refer to 5.2.3 special function register (sfr) table 5-5. special function register list .) caution do not access addresses where the sfr is not assigned. 5.1.4 external memory space the external memory space is accessible with memory expansion mode register. external memory space can store program, table data, etc., and allocate peripheral devices.
95 chapter 5 cpu architecture 5.1.5 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. the address of an instruction to be executed next is addressed by the program counter (pc) (for details, see 5.3 instruction address addressing ). several addressing modes are provided for addressing the memory relevant to the execution of instructions for the m pd780024, 780034, 780024y, and 780034y subseries, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. data memory addressing is illustrated in figures 5-6 to 5-10. for the details of each addressing mode, see 5.4 operand address addressing . figure 5-6. data memory addressing ( m pd780021, 780031, 780021y, 780031y) 0000h general registers 32 8 bits internal rom 8192 8 bits external memory 55296 8 bits 2000h 1fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits reserved fd00h fcffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
96 chapter 5 cpu architecture figure 5-7. data memory addressing ( m pd780022, 780032, 780022y, 780032y) 0000h general registers 32 ? 8 bits internal rom 16384 ? 8 bits external memory 47104 ? 8 bits 4000h 3fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 ? 8 bits reserved fd00h fcffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 ? 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
97 chapter 5 cpu architecture figure 5-8. data memory addressing ( m pd780023, 780033, 780023y, 780033y) 0000h general registers 32 8 bits internal rom 24576 8 bits external memory 38912 8 bits 6000h 5fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
98 chapter 5 cpu architecture figure 5-9. data memory addressing ( m pd780024, 780034, 780024y, 780034y) 0000h general registers 32 8 bits internal rom 32768 8 bits external memory 30720 8 bits 8000h 7fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
99 chapter 5 cpu architecture figure 5-10. data memory addressing ( m pd78f0034, 78f0034y) 0000h general registers 32 8 bits flash memory 32768 8 bits external memory 30720 8 bits 8000h 7fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
100 chapter 5 cpu architecture 5.2 processor registers the m pd780024, 780034, 780024y, 780034y subseries products incorporate the following processor registers. 5.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 5-11. program counter format 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 5-12. program status word format 70 psw ie z rbs1 ac rbs0 0 isp cy
101 chapter 5 cpu architecture (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie is set to the disable interrupt (di) state, and only non-maskable interrupt request becomes acknowledgeable. other interrupt requests are all disabled. when 1, the ie is set to the enable interrupt (ei) state and interrupt request acknowledge enable is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources and a priority specification flag. the ie is reset to (0) upon di instruction execution or interrupt acknowledgement and is set to (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when this flag is 0, low- level vectored interrupts request specified with a priority specify flag register (pr0l, pr0h, pr1l) (refer to 19.3 (3) priority specify flag register (pr0l, pr0h, pr1l) ) are disabled for acknowledgement. when it is 1, all interrupts are acknowledgeable. actual request acknowledgement is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. the internal high-speed ram areas of each product are as follows. table 5-4. internal high-speed ram area product internal high-speed ram area m pd780021, 780031, 780021y, 780031y fd00h to feffh m pd780022, 780032, 780022y, 780032y m pd780023, 780033, 780023y, 780033y fb00h to feffh m pd780024, 780034, 780024y, 780034y m pd78f0034, 78f0034y
102 chapter 5 cpu architecture figure 5-13. stack pointer format 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 5-14 and 5-15. caution since reset input makes sp contents undefined, be sure to initialize the sp before instruction execution. figure 5-14. data to be saved to stack memory figure 5-15. data to be restored from stack memory interrupt and brk instructions psw pc15-pc8 pc15-pc8 pc7-pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7-pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti and retb instructions psw pc15-pc8 pc15-pc8 pc7-pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7-pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3
103 chapter 5 cpu architecture 5.2.2 general registers a general register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can also be used as an 8-bit register. two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. figure 5-16. general register configuration (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h
104 chapter 5 cpu architecture 5.2.3 special function register (sfr) unlike a general register, each special-function register has special functions. it is allocated in the ff00h to ffffh area. the special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions. manipulatable bit units, 1, 8, and 16, depend on the special-function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 5-5 gives a list of special-function registers. the meaning of items in the table is as follows. ? symbol symbol indicating the address of a special function register. it is a reserved word in the ra78k/0, and is defined via the header file sfrbit.h in the cc78k/0. when using the ra78k/0, id78k0-ns, id78k0, or sm78k0, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding special-function register can be read or written. r/w : read/write enable r : read only w : write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). - indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset input.
105 chapter 5 cpu architecture address special-function register (sfr) name symbol r/w after reset ff00h port0 p0 r/w ? 00h ff01h port1 p1 r ? ff02h port2 p2 r/w ? ff03h port3 p3 ? ff04h port4 p4 ? ff05h port5 p5 ? ff06h port6 p6 ? ff07h port7 p7 ? ff0ah capture/compare register 00 cr00 undefined ff0bh ff0ch capture/compare register 01 cr01 ff0dh ff0eh 16-bit timer register tm0 r 0000h ff0fh ff10h 8-bit compare register 50 cr50 r/w undefined ff11h 8-bit compare register 51 cr51 ff12h 8-bit counter 50 tm5 tm50 r ? 00h ff13h 8-bit counter 51 tm51 ff16h a/d conversion result register 0 adcr0 note 1 note 2 ff17h ff18h transmit shift register txs0 w ffh receive buffer register rxb0 r ff1ah serial i/o shift register 30 sio30 r/w undefined ff1bh serial i/o shift register 31 note 3 sio31 ff1fh iic shift register note 4 iic0 00h table 5-5. special function register list (1/3) manipulatable bit unit 8 bits 1 bit 16 bits notes 1. m pd780024, 780024y subseries only 2. m pd780034, 780034y subseries only, 16-bit access possible 3. m pd780024, 780034 subseries only 4. m pd780024y, 780034y subseries only
106 chapter 5 cpu architecture address special-function register (sfr) name symbol r/w after reset ff20h port mode register 0 pm0 r/w ? ffh ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ff24h port mode register 4 pm4 ? ff25h port mode register 5 pm5 ? ff26h port mode register 6 pm6 ? ff27h port mode register 7 pm7 ? ff30h pull-up resistor option register 0 pu0 ? 00h ff32h pull-up resistor option register 2 pu2 ? ff33h pull-up resistor option register 3 pu3 ? ff34h pull-up resistor option register 4 pu4 ? ff35h pull-up resistor option register 5 pu5 ? ff36h pull-up resistor option register 6 pu6 ? ff37h pull-up resistor option register 7 pu7 ? ff40h clock output selection register cks ? ff41h watch timer mode control register wtm ? ff42h watchdog timer clock selection register wdcs ff47h memory expansion mode register mem ? ff48h external interrupt rising edge enable register egp ? ff49h external interrupt falling edge enable register egn ? ff60h 16-bit timer mode control register tmc0 ? ff61h prescaler mode register prm0 ff62h capture/compare control register 0 crc0 ? ff63h 16-bit timer output control register 0 toc0 ? ff70h 8-bit timer mode control register 50 tmc50 ? 04h ff71h timer clock selection register 50 tcl50 00h ff78h 8-bit timer mode control register 51 tmc51 ? 04h ff79h timer clock selection register 51 tcl51 00h ff80h a/d converter mode register adm0 ? ff81h analog input channel specification register ads0 ffa0h asynchronous serial interface mode register asim0 ? ffa1h asynchronous serial interface status register asis0 r ffa2h baud rate generator control register brgc0 r/w table 5-5. special-function register list (2/3) manipulatable bit unit 8 bits 16 bits 1 bit
107 chapter 5 cpu architecture address special-function register (sfr) name symbol r/w after reset ffa8h iic control register note 1 iicc0 r/w ? 00h ffa9h iic status register note 1 iics0 r ? ffaah iic clock selection register note 1 iiccl0 r/w ? ffabh slave address register note 1 sva0 ffb0h serial operation mode register 30 csim30 ? ffb8h serial operation mode register 31 note 2 csim31 ? ffd0h external access area note 3 ? undefined ? ffdfh ffe0h interrupt request flag register 0l if0 if0l ?? 00h ffe1h interrupt request flag register 0h if0h ? ffe2h interrupt request flag register 1l if1l ? ffe4h interrupt mask flag register 0l mk0 mk0l ?? ffh ffe5h interrupt mask flag register 0h mk0h ? ffe6h interrupt mask flag register 1l mk1l ? ffe8h priority level specification flag register 0l pr0 pr0l ?? ffe9h priority level specification flag register 0h pr0h ? ffeah priority level specification flag register 1l pr1l ? fff0h memory size switching register ims cfh note 4 fff8h memory expansion wait setting register mm ? 10h fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time selection register osts 04h fffbh processor clock control register pcc ? table 5-5. special-function register list (3/3) manipulatable bit unit 16 bits 8 bits 1 bit notes 1. m pd780024y, 780034y subseries only 2. m pd780024, 780034 subseries only 3. the external access area cannot be accessed by sfr addressing. access it with the direct addressing method. 4. the default is cfh, but set the value corresponding to each respective product as indicated below. m pd780021, 780031, 780021y, 780031y: 42h m pd780022, 780032, 780022y, 780032y: 44h m pd780023, 780033, 780023y, 780033y: c6h m pd780024, 780034, 780024y, 780034y: c8h m pd78f0034, 780034y: value for mask rom version
108 chapter 5 cpu architecture 5.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing. (for details of instructions, refer to 78k/0 users manual C instructions (u12326e) . 5.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed twos complement data (C128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists in relative branching from the start address of the following instruction to the C128 to +127 range. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc a jdisp8 when s = 0, all bits of a are 0. when s = 1, all bits of a are 1. pc indicates the start address of the instruction after the br instruction. ...
109 chapter 5 cpu architecture 5.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branched to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10? 11 10 00001 643 callf fa 7? 15 0 pc 87 70 call or br low addr. high addr.
110 chapter 5 cpu architecture 5.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. this instruction references the address stored in the memory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4? operation code
111 chapter 5 cpu architecture 5.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
112 chapter 5 cpu architecture 5.4 operand address addressing the following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 implied addressing [function] the register which functions as an accumulator (a and ax) in the general register is automatically (implicitly) addressed. of the m pd780024, 780034, 780024y, 780034y subseries instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
113 chapter 5 cpu architecture 5.4.2 register addressing [function] the general register to be specified is accessed as an operand with the register specify code (rn and rpn) of an instruction word in the registered bank specified with the register bank select flag (rbs0 to rbs1). register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 01100010 register specify code incw de; when selecting de register pair as rp operation code 10000100 register specify code
114 chapter 5 cpu architecture 5.4.3 direct addressing [function] the memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code
115 chapter 5 cpu architecture 5.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. an internal ram and a special-function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. if the sfr area (ff00h to ff1fh) where short direct addressing is applied, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to the [illustration] on the next page. [operand format] identifier description saddr label of fe20h to ff1fh immediate data saddrp label of fe20h to ff1fh immediate data (even address only)
116 chapter 5 cpu architecture [description example] mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h operation code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) [illustration] when 8-bit immediate data is 20h to ffh, a = 0 when 8-bit immediate data is 00h to 1fh, a = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset a
117 chapter 5 cpu architecture 5.4.5 special-function register (sfr) addressing [function] the memory-mapped special-function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special-function register name sfrp 16-bit manipulatable special-function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op code 00100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
118 chapter 5 cpu architecture 5.4.6 register indirect addressing [function] register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory to be manipulated. this addressing can be carried out for all the memory spaces. [operand format] identifier description [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de
119 chapter 5 cpu architecture 5.4.7 based addressing [function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flag (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000
120 chapter 5 cpu architecture 5.4.8 based indexed addressing [function] the b or c register contents specified in an instruction are added to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flag (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] operation code 10101011 5.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. [description example] in the case of push de operation code 10110101
121 chapter 6 port functions 6.1 port functions the m pd780024, 780034, 780024y, and 780034y subseries products incorporate eight input ports and forty-three input/output ports. figure 6-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on- chip hardware input/output pins. figure 6-1. port types ? ? ? port 0 p00 port 1 p10 p17 port 2 p20 p25 port 3 p30 p36 port 6 port 5 p50 p57 p64 p67 port 7 p70 p75 port 4 p40 p47 p03
122 chapter 6 port functions table 6-1. port functions ( m pd780024, 780034 subseries) alternate function intp0 intp1 intp2 intp3/adtrg ani0 to ani7 si30 so30 sck30 rxd0 txd0 asck0 si31 so31 sck31 ad0 to ad7 a8 to a15 rd wr wait astb ti00/to0 ti01 ti50/to50 ti51/to51 pcl buz pin name p00 p01 p02 p03 p10 to p17 p20 p21 p22 p23 p24 p25 p30 p31 p32 p33 p34 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 p70 p71 p72 p73 p74 p75 function port 0 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 1 8-bit input only port. port 2 6-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 3 n-ch open-drain input/output port. 7-bit input/output port. on-chip pull-up resistor can be specified by mask input/output mode can be specified option (mask version only). bit-wise. leds can be driven directly. if used as an input port, an on-chip pull-up resistor can be specified by software. port 4 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be specified by software. interrupt request flag (krif) is set to 1 by falling edge detection. port 5 8-bit input/output port. leds can be driven directly. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 6 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 7 6-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software.
123 chapter 6 port functions table 6-2. port functions ( m pd780024y, 780034y subseries) alternate function intp0 intp1 intp2 intp3/adtrg ani0 to ani7 si30 so30 sck30 rxd0 txd0 asck0 sda0 scl0 ad0 to ad7 a8 to a15 rd wr wait astb ti00/to0 ti01 ti50/to50 ti51/to51 pcl buz pin name p00 p01 p02 0p3 p10 to p17 p20 p21 p22 p23 p24 p25 p30 p31 p32 p33 p34 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 p70 p71 p72 p73 p74 p75 function port 0 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 1 8-bit input only port. port 2 6-bit input/output port input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be used by software. port 3 n-ch open-drain input/output port. 7-bit input/output port. on-chip pull-up resistor can be specified by mask input/output mode can be specified option (p30 and p31 are mask rom version only). bit-wise. leds can be driven directly. if used as an input port, pull-up resistor can be used by software. port 4 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, pull-up resistor can be used by software. interrupt request flag (krif) is set to 1 by falling edge detection. port 5 8-bit input/output port. leds can be driven directly. input/output mode can be specified bit-wise. if used as an input port, pull-up resistor can be used by software. port 6 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, pull-up resistor can be used by software. port 7 6-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software.
124 chapter 6 port functions 6.2 port configuration a port consists of the following hardware: table 6-3. port configuration item configuration control register port mode register (pmm: m = 0, 2 to 7) pull-up resistor option register (puom,: m = 0, 2 to 7) port total: 51 ports (8 inputs, 43 inputs/outputs) pull-up resistor ? mask rom version total: 43 (software specifiable: 39, mask option: 4) ? flash memory version total: 39 6.2.1 port 0 port 0 is a 4-bit input/output port with output latch. p00 to p03 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (pm0). when p00 to p03 pins are used as input ports, an on-chip pull-up resistor can be used to them in 6-bit units with a pull-up resistor option register 0 (pu0). this port can also be used as an external interrupt request input, and a/d converter external trigger input. reset input sets port 0 to input mode. figures 6-2 show block diagrams of port 0. caution because port 0 also serves for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1.
125 chapter 6 port functions figure 6-2. p00 to p03 configurations rd p00/intp0 to p02/intp2, p03/intp3/adtrg p-ch wr puo wr port wr pm pu00 to pu03 output latch (p00 to p03) pm00 to pm03 selector v dd0 internal bus pu : pull-up resistor option register pm : port mode register rd : port 0 read signal wr : port 0 write signal 6.2.2 port 1 port 1 is an 8-bit input only port. this port can also be used as an a/d converter analog input. figure 6-3 shows a block diagram of port 1. figure 6-3. p10 to p17 configurations rd p10/ani0 to p17/ani7 internal bus rd : port 1 read signal
126 chapter 6 port functions 6.2.3 port 2 port 2 is a 6-bit input/output port with output latch. p20 to p25 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (pm2). when p20 to p25 pins are used as input ports, an on-chip pull-up resistor can be used for them in 1-bit units with a pull-up resistor option register 2 (pu2). this port has also alternate functions as serial interface data input/output and clock input/output. reset input sets port 2 to input mode. figure 6-4 shows a block diagram of port 2. figure 6-4. p20 to p25 configurations rd p20/si30, p21/so30, p22/sck30, p23/rxd0, p24/txd0, p25/asck0 p-ch wr puo wr port wr pm pu20 to pu25 output latch (p20 to p25) pm20 to pm25 selector v dd0 internal bus alternate functions pu : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal
127 chapter 6 port functions 6.2.4 port 3 ( m pd780024, 780034 subseries) port 2 is a 7-bit input/output port with output latch. p30 to p36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (pm3). this port has the following functions for pull-up resistors. these functions differ depending on the board's higher 36-bit/lower 4-bit, and whether the products is a mask rom version or a flash memory version. table 6-4. pull-up resistor of port 3 ( m pd780024, 780034 subseries) higher 3-bit (p34 to p36 pins) lower 4-bit (p30 to p33 pins) mask rom version an on-chip pull-up resistor on-chip pull-up resistor can be specified can be used bit-wise by pu3 bit-wise by mask option flash memory version on-chip pull-up resistor is not provided pu3: pull-up resistor option register 3 the p30 to p33 pins can drive leds directly. the p34 to p36 pins can also be used for serial interface data input/output and clock input/output. reset input sets port 3 to input mode. figures 6-5 and 6-6 show a block diagram of port 3. figure 6-5. p30 to p33 configurations ( m pd780024, 780034 subseries) pm : port mode register rd : port 3 read signal wr : port 3 write signal rd p30 to p33 wr port wr pm output latch (p30 to p33) pm30 to pm33 selector v dd0 mask option register ? internal bus mask rom version only no pull-up register for flash memory version
128 chapter 6 port functions figure 6-6. p34 to p36 configurations ( m pd780024, 780034 subseries) rd p34/si31, p35/sc31, p36/sck31 p-ch wr puo wr port wr pm pu34 to pu36 output latch (p34 to p36) pm34 to pm36 selector v dd0 internal bus pu : pull-up resistor option register pm : port mode register rd : port 3 read signal wr : port 3 write signal
129 chapter 6 port functions 6.2.5 port 3 ( m pd780024y, 780034y subseries) port 3 is a 7-bit input/output port with output latch. p30 to p36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (pm3). this port has the following functions for pull-up resistors. these functions differ depending on bits location and mask rom version/flash memory version. table 6-5. pull-up resistor of port 3 ( m pd780024y, 780034y subseries) p34 to p36 pins p30, p31 pins mask rom version a pull-up resistor can be on-chip pull-up resistor can be specified connected bit-wise by pu3 bit-wise by mask option flash memory version on-chip pull-up resistor is not be specified pu3: pull-up resistor option register 3 caution p32, p33 pins have no pull-up resistor. the p30 to p33 pins can drive leds directly. the p32 and p33 pins can also be used for interface data input/output and clock input/output. reset input sets port 3 to input mode. figures 6-7 through 6-9 show the block diagram of port 3.
130 chapter 6 port functions figure 6-7. p30 and p31 configurations ( m pd780024y, 780034y subseries) pm : port mode register rd : port 3 read signal wr : port 3 write signal figure 6-8. p32 and p33 configurations ( m pd780024y, 780034y subseries) rd p32/sda0, p33/scl0 wr port wr pm output latch (p32, p33) pm32, pm33 selector internal bus pm : port mode register rd : port 3 read signal wr : port 3 write signal rd p30, p31 wr port wr pm output latch (p30, p31) pm30, pm31 selector v dd0 mask option resistor mask rom versions only no pull-up resistor for flash memory versions internal bus
131 chapter 6 port functions figure 6-9. p34 to p36 configurations ( m pd780024y, 780034y subseries) rd p34 to p36 p-ch wr puo wr port wr pm pu34 to pu36 output latch (p34 to p36) pm34 to pm36 selector v dd0 internal bus pu : pull-up resistor option register pm : port mode register rd : port 6 read signal wr : port 6 write signal
132 chapter 6 port functions 6.2.6 port 4 port 4 is an 8-bit input/output port with output latch. the p40 to p47 pins can specify the input mode/output mode in 1-bit units with port mode register 4 (pm4). when the p40 to p47 pins are used as input ports, a pull-up resistor can be connected to them in 1-bit units with pull-up resistor option register 4 (pu4). the interrupt request flag (krif) can be set to 1 by detecting falling edges. this port can also be used as an address/data bus in external memory expansion mode. reset input sets port 4 to input mode. figures 6-10 and 6-11 show a block diagram of port 4 and block diagram of the falling edge detection circuit, respectively. figure 6-10. p40 to p47 configurations rd p40/ad0 to p47/ad7 p-ch wr puo wr port wr pm pu40 to pu47 output latch (p40 to p47) pm40 to pm47 selector v dd0 internal bus puo : pull-up resistor option register pm : port mode register rd : port 4 read signal wr : port 4 write signal figure 6-11. falling edge detection circuit block diagram p40 p41 p42 p43 p44 p45 p46 p47 intkr falling edge detection circuit
133 chapter 6 port functions 6.2.7 port 5 port 5 is an 8-bit input/output port with output latch. the p50 to p57 pins can specify the input mode/output mode in 1-bit units with port mode register 5 (pm5). when the p50 to p57 pins are used as input ports, an on-chip pull- up resistor can be used for them in 1-bit units with pull-up resistor option register 5 (pu5). port 5 can drive leds directly. this port can also be used as an address bus in external memory expansion mode. reset input sets port 5 to input mode. figure 6-12 shows a block diagram of port 5. figure 6-12. p50 to p57 configurations rd p50/a8 to p57/a15 p-ch wr puo wr port wr pm pu50 to pu57 output latch (p50 to p57) pm50 to pm57 selector v dd0 internal bus pu : pull-up resistor option register pm : port mode register rd : port 5 read signal wr : port 5 write signal
134 chapter 6 port functions 6.2.8 port 6 port 6 is a 4-bit input/output port with output latch. the p64 to p67 pins can specify the input mode/output mode in 1-bit units with port mode register 6 (pm6). when pins p64 to p67 are used as input ports, an on-chip pull-up resistor can be used for them in 1-bit units with pull-up resistor option register 6 (pu6). this port can also be used as a control signal output in external memory expansion mode. reset input sets port 6 to input mode. figures 6-13 shows a block diagram of port 6. caution when external wait is not used in external memory expansion mode, p66 can be used as an input/output port. figure 6-13. p64 to p67 configurations rd p64/rd, p65/wr, p66/wait, p67/astb p-ch wr puo wr port wr pm pu64 to pu67 output latch (p64 to p67) pm64 to pm67 selector v dd0 internal bus pu : pull-up resistor option register pm : port mode register rd : port 6 read signal wr : port 6 write signal
135 chapter 6 port functions 6.2.9 port 7 this is a 6-bit input/output port with output latches. input mode/output mode can be specified bit-wise by means of port mode register 7 (pm7). when pins p70 to p75 are used as input port pins, an on-chip pull-up resistor can be used as a 1-bit unit by means of pull-up resistor option register 7 (pu7). this port can also be used as a timer input/output, clock output, and buzzer output. reset input sets the input mode. figure 6-14 shows a block diagram of port 7. figure 6-14. p70 to p75 configurations rd p70/ti00/to0, p71/ti01, p72/ti50/to50, p73/ti51/to51, p74/pcl, p75/buz p-ch wr puo wr port wr pm pu70 to pu75 pm70 to pm75 selector v dd0 alternate functions output latch (p70 to p75) internal bus pu : pull-up resistor option register pm : port mode register rd : port 7 read signal wr : port 7 write signal
136 chapter 6 port functions 6.3 port function control registers the following two types of registers control the ports. ? port mode registers (pm0, pm2 to pm7) ? pull-up resistor option register (pu0, pu2 to pu7) (1) port mode registers (pm0, pm2 to pm7) these registers are used to set port input/output in 1-bit units. pm0 and pm2 to pm7 are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets registers to ffh. cautions 1. pins p10 and p17 are input-only pins. 2. as port 0 has an alternate function as an external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.
137 chapter 6 port functions figure 6-15. port mode register (pm0, pm2 to pm7) format address: ff20h after reset : ffh r/w symbol 7 6 5 43210 pm0 1 1 1 1 pm03 pm02 pm01 pm00 address: ff22h after reset : ffh r/w symbol 7 6 5 43210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 address: ff23h after reset : ffh r/w symbol 7 6 5 43210 pm3 1 pm36 pm35 pm34 pm33 pm32 pm31 pm30 address: ff24h after reset : ffh r/w symbol 7 6 5 43210 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 address: ff25h after reset : ffh r/w symbol 7 6 5 43210 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 address: ff26h after reset : ffh r/w symbol 7 6 5 43210 pm6 pm67 pm66 pm65 pm64 1111 address: ff27h after reset : ffh r/w symbol 7 6 5 43210 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pmmn pmn pin input/output mode select (m = 0, 2 to 7: n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
138 chapter 6 port functions (2) pull-up resistor option register (pu0, pu2 to pu7) this register is used to set whether to use an internal pull-up resistor at each port or not. a pull-up resistor is internally used at bits which are set to the input mode at a port where pull-up resistor use has been specified with pu0, pu2 to pu7. no pull-up resistors can be used to the bits set to the output mode, irrespective of the pu0 or pu2 to pu7 setting. pu0 and pu2 to pu7 are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. cautions 1. the p10 and p17 pins do not incorporate a pull-up resistor. 2. when ports 4 and 6 pins are used as alternate function pins, a pull-up resistor cannot be used even if 1 is set in pumn (m = 0, 2 to 7: n = 0 to 7). 3. pins p30 to p33 (in m pd780024y and 780034y subseries, p30 and p31 pins) can be used with pull-up resistor by mask option only for mask rom version.
139 chapter 6 port functions figure 6-16. pull-up resistor option register (pu0, pu2 to pu7) format address: ff30h after reset : 00h r/w symbol 7 6 5 43210 pu0 0 0 0 0 pu03 pu02 pu01 pu00 address: ff32h after reset : 00h r/w symbol 7 6 5 43210 pu2 0 0 pu25 pu24 pu23 pu22 pu21 pu20 address: ff33h after reset : 00h r/w symbol 7 6 5 43210 pu3 0 pu36 pu35 pu34 0000 address: ff34h after reset : 00h r/w symbol 7 6 5 43210 pu4 pu47 pu46 pu45 pu44 pu43 pu42 pu41 pu40 address: ff35h after reset : 00h r/w symbol 7 6 5 43210 pu5 pu57 pu56 pu55 pu54 pu53 pu52 pu51 pu50 address: ff36h after reset : 00h r/w symbol 7 6 5 43210 pu6 pu67 pu66 pu65 pu64 0000 address: ff37h after reset : 00h r/w symbol 7 6 5 43210 pu7 0 0 pu75 pu74 pu73 pu72 pu71 pu70 pumn pmn pin internal pull-up resistor select (m = 0, 2 to 7: n = 0 to 7) 0 on-chip pull-up resistor not used 1 on-chip pull-up resistor used
140 chapter 6 port functions 6.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 writing to input/output port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 6.4.2 reading from input/output port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 6.4.3 operations on input/output port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
141 chapter 6 port functions 6.5 selection of mask option the following mask option is provided in the mask rom version. the flash memory versions have no mask options. table 6-6. comparison between mask rom version and flash memory version pin name mask rom version flash memory version mask option for pins p30 to p33 note bit-wise selectable on-chip pull-up resistors no on-chip pull-up resistor note for m pd780024y and 780034y subseries products, only the p30 and p31 pins can incorporate a pull-up resistor.
142 [memo]
143 chapter 7 clock generator 7.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are available. (1) main system clock oscillator this circuit oscillates at frequencies of 1 to 8.38 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). (2) subsystem clock oscillator the circuit oscillates at a frequency of 32.768 khz. oscillation cannot be stopped. if the subsystem clock oscillator is not used, the internal feedback resistor can be disabled by the processor clock control register (pcc). this enables to reduce the power dissipation in the stop mode. 7.2 clock generator configuration the clock generator consists of the following hardware. table 7-1. clock generator configuration item configuration control register processor clock control register (pcc) oscillator main system clock oscillator subsystem clock oscillator
144 chapter 7 clock generator figure 7-1. clock generator block diagram frc subsystem clock oscillator f xt x1 x2 main system clock oscillator f x prescaler f x 2 f x 2 2 f x 2 3 f x 2 4 f xt 2 1/2 prescaler watch timer clock output function clock to peripheral hardware cpu clock (f cpu ) standby control circuit wait control circuit to intp0 sampling clock 3 stop mcc frc cls css pcc2 pcc1 pcc0 processor clock control register (pcc) internal bus selector xt1 xt2
145 chapter 7 clock generator 7.3 clock generator control register the clock generator is controlled by the processor clock control register (pcc). the pcc sets whether to use cpu clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor. the pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the pcc to 04h. figure 7-2. subsystem clock feedback resistor frc p-ch feedback resistor xt1 xt2
146 chapter 7 clock generator figure 7-3. processor clock control register (pcc) format address: fffbh after reset: 04h r/w note 1 symbol 76543210 pcc mcc frc cls css 0 pcc2 pcc1 pcc0 mcc main system clock oscillation control note 2 0 oscillation possible 1 oscillation stopped frc subsystem clock feedback resistor select 0 internal feedback resistor used 1 internal feedback resistor not used cls cpu clock status 0 main system clock 1 subsystem clock css pcc2 pcc1 pcc0 cpu clock (f cpu ) select 0000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 1000f xt /2 001 010 011 100 other than above setting prohibited notes 1. bit 5 is read only. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the main system clock oscillation. a stop instruction should not be used. cautions 1. bit 3 must be set to 0. 2. when the external clock is input, mcc should not be set. this is because the x2 pin is connected to v dd1 via a pull-up resistor. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
147 chapter 7 clock generator the fastest instructions of m pd780024, 780034, 780024y, and 780034y subseries are carried out in 2 cpu clocks. the relationship of cpu clock (f cpu ) and minimum instruction execution time is shown in table 7-2. table 7-2 relationship of cpu clock and min. instruction execution time cpu clock (f cpu ) min. instruction execution time: 2/(f cpu ) f x 0.24 m s f x 2 0.48 m s f x 2 2 0.95 m s f x 2 3 1.91 m s f x 2 4 3.81 m s f xt 2 122 m s f x = 8.38 mhz, f xt = 32.768 khz f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 7.4 system clock oscillator 7.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.38 mhz) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and an inversed-phase clock signal to the x2 pin. figure 7-4 shows an external circuit of the main system clock oscillator. figure 7-4. external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock crystal resonator or ceramic resonator x2 x1 pd74hcu04 external clock x2 x1 ic m v ss1 caution do not execute the stop instruction and do not set mcc [bit 7 of processor clock control register (pcc)] to 1 if an external clock is input. this is because when the stop instruction or mcc is set to 1, the main system clock operation stops and the x2 pin is connected to v dd1 via a pull-up resistor.
148 chapter 7 clock generator 7.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the xt1 pin and an inversed-phase clock signal to the xt2 pin. figure 7-5 shows an external circuit of the subsystem clock oscillator. figure 7-5. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 ic xt1 32.768 khz xt1 xt2 pd74hcu04 external clock m v ss1 cautions are listed on the next page.
149 chapter 7 clock generator cautions 1. when using the main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in figures 7-4 and 7-5 to prevent any effects from wiring capacitance. ? minimize the wiring length. ? do not allow wiring to intersect with other signal lines. do not route the wiring in the vicinity of a line through which a high-fluctuating current flows. ? always keep the ground of the capacitor of the oscillation circuit at the same potential as v ss1 . do not ground a capacitor to a ground pattern where high-current flows. ? do not fetch signals from the oscillator. take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. figure 7-6 shows examples of incorrect oscillator connection. figure 7-6. examples of incorrect oscillator connection (1/2) (a) too long wiring (b) crossed signal line x1 ic x2 x2 ic x1 portn (n = 0-7) v ss1 v ss1 remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. further, insert resistors in series on the side of xt2.
150 chapter 7 clock generator figure 7-6. examples of incorrect oscillator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) ic x2 x1 ic x2 x1 ab c pmn v dd0 high current high current v ss1 v ss1 (e) signals are fetched ic x2 x1 v ss1 remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. cautions 2. when x2 and xt1 are wired in parallel, the cross-talk noise of x2 may increase with xt1, resulting in malfunctioning. to prevent that from occurring, it is recommended to wire x2 and xt1 so that they are not in parallel, and to connect the ic pin between x2 and xt1 directly to v ss1 .
151 chapter 7 clock generator 7.4.3 scaler the scaler divides the main system clock oscillator output (f x ) and generates various clocks. 7.4.4 when no subsystem clocks are used if it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the xt1 and xt2 pins as follows. xt1 : connect to v dd0 xt2 : open in this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. to minimize leakage current, the above internal feedback resistor can be removed with bit 6 (frc) of the processor clock control register (pcc). in this case also, connect the xt1 and xt2 pins as described above.
152 chapter 7 clock generator 7.5 clock generator operations the clock generator generates the following various types of clocks and controls the cpu operating mode including the standby mode. ? main system clock f x ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the following clock generator functions and operations are determined with the processor clock control register (pcc). (a) upon generation of reset signal, the lowest speed mode of the main system clock (3.81 m s @ 8.38-mhz oscillation) is selected (pcc = 04h). main system clock oscillation stops while low level is applied to reset pin. (b) with the main system clock selected, one of the five cpu clock types (0.24 m s. 0.48 m s, 0.95 m s, 1.91 m s, 3.81 m s, @ 8.38-mhz operation) can be selected by setting the pcc. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. to reduce current consumption in the stop mode, the subsystem clock feedback resistor can be disconnected to stop the subsystem clock. (d) the pcc can be used to select the subsystem clock and to operate the system with low-current consumption (122 m s @ 32.768-khz operation). (e) with the subsystem clock selected, main system clock oscillation can be stopped with the pcc. the halt mode can be used. however, the stop mode cannot be used. (subsystem clock oscillation cannot be stopped.) (f) the main system clock is divided and supplied to the peripheral hardware. the subsystem clock is supplied to the watch timer and clock output functions only. thus the watch function and the clock output function can also be continued in the standby state. however, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stops if the main system clock is stopped. (except external input clock operation)
153 chapter 7 clock generator 7.5.1 main system clock operations when operated with the main system clock (with bit 5 (cls) of the processor clock control register (pcc) set to 0), the following operations are carried out by pcc setting. (a) because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) if bit 7 (mcc) of the pcc is set to 1 when operated with the main system clock, the main system clock oscillation does not stop. when bit 4 (css) of the pcc is set to 1 and the operation is switched to subsystem clock operation (cls = 1) after that, the main system clock oscillation stops (see figure 7-7 ). figure 7-7. main system clock stop function (1/2) (a) operation when mcc is set after setting css with main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock (b) operation when mcc is set in case of main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock l l oscillation does not stop.
154 chapter 7 clock generator figure 7-7. main system clock stop function (2/2) (c) operation when css is set after setting mcc with main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock 7.5.2 subsystem clock operations when operated with the subsystem clock (with bit 5 (cls) of the processor clock control register (pcc) set to 1), the following operations are carried out. (a) the minimum instruction execution time remains constant (122 m s @ 32.768-khz operation) irrespective of bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) watchdog timer counting stops. caution do not execute the stop instruction while the subsystem clock is in operation. 7.6 changing system clock and cpu clock settings 7.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by means of bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc, but operation continues on the pre-switchover clock for several instructions (see table 7-3 ). determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (cls) of the pcc register.
155 chapter 7 clock generator table 7-3. maximum time required for cpu clock switchover set value before set value after switchover switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0000 00 01001000 1101001 0000 16 instructions 16 instructions 16 instructions 16 instructions f x /2f xt instruction (77 instructions) 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions f x /4f xt instruction (39 instructions) 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions f x /8f xt instruction (20 instructions) 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions f x /16f xt instruction (10 instructions) 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction f x /32f xt instruction (5 instructions) 1 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction remarks 1. one instruction is the minimum instruction execution time with the pre-switchover cpu clock. 2. figures in parentheses are for operation with f x = 8.38 mhz and f xt = 32.768 khz. caution selection of the cpu clock cycle scaling factor (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be set simulta- neously. simultaneous setting is possible, however, for selection of the cpu clock cycle scaling factor (pcc0 to pcc2) and switch over from the subsystem clock to the main system clock (changing css from 1 to 0).
156 chapter 7 clock generator 7.6.2 system clock and cpu clock switching procedure this section describes switching procedure between the system clock and cpu clock. figure 7-8. system clock and cpu clock switching system clock cpu clock interrupt request signal reset v dd f x f x f xt f x lowest- speed operation highest- speed operation subsystem clock operation high-speed operation wait (15.6 ms: @8.38-mhz operation) internal reset operation <1> the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, main system clock starts oscillation. at this time, oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing the instruction at the minimum speed of the main system clock (3.81 m s @ 8.38-mhz operation). <2> after the lapse of a sufficient time for the v dd voltage to increase to enable operation at maximum speeds, the pcc is rewritten and maximum-speed operation is carried out. <3> upon detection of a decrease of the v dd voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). <4> upon detection of v dd voltage reset due to an interrupt, 0 is set to the mcc and oscillation of the main system clock is started. after the lapse of time required for stabilization of oscillation, the pcc is rewritten and the maximum-speed operation is resumed. caution when subsystem clock is being operated while the main system clock is stopped, if switching to the main system clock is done again, be sure to switch after securing oscillation stabilization time by software.
157 chapter 8 16-bit timer/event counter 8.1 outline of timer integrated in m pd780024, 780034, 780024y, 780034y subseries in this chapter, the 16-bit timer/event counter is described. the timers integrated in the m pd780024, 780034, 780024y, and 780034y subseries are outlined below. (1) 16-bit timer/event counter (tm0) the tm0 can be used as an interval timer, pulse widths measurement (infrared ray remote control receive function), external event counter, square wave output of any frequency, or one-shot pulse output. (2) 8-bit timer/event counter (tm5) the tm5 can be used to serve as an interval timer, an external event counter, to output square wave output with any selected frequency, and pwm output. two 8-bit timer/event counters can be used as one 16-bit timer/event counter (see chapter 9 8-bit timer/event counter ). (3) watch timer (wt) this timer can set a flag every 0.5 sec. or 0.25 sec. and simultaneously generate an interrupt request at the preset time intervals (see chapter 10 watch timer ). (4) watchdog timer (wdt) the watchdog timer can also be used to generate a non-maskable interrupt request, maskable interrupt request, or reset signal at the preset time intervals (see chapter 11 watchdog timer ). (5) clock output/buzzer output control circuit (cku) the clock output circuit supplies other devices with the divided main system clock and the subsystem clock, and buzzer output supplies the buzzer frequency with the divided main system clock (see chapter 12 clock output/buzzer output control circuits ).
158 chapter 8 16-bit timer/event counter table 8-1. timer/event counter operations 16-bit timer/ 8-bit timer/ watch timer watchdog timer event counter event counter operation interval timer 2 channels note3 2 channels 1 channel note1 1 channel note2 mode external event counter ? CC function timer output ? CC pwm output C CC pulse width measurement CCC square-wave output ? CC one-shot pulse output CCC interrupt request ? notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. wdtm can perform either the watchdog timer function or the interval timer function. 3. when capture/compare registers 00, 01 (cr00, cr01) are specified as compare registers. 8.2 16-bit timer/event counter functions the 16-bit timer/event counter has the following functions. ? interval timer ? ppg output ? pulse width measurement ? external event counter ? square-wave output ? one-shot pulse output figure 8-1 shows 16-bit timer/event counter block diagram.
159 chapter 8 16-bit timer/event counter figure 8-1. 16-bit timer/event counter block diagram internal bus capture/compare control register 0 (crc0) ti01/p71 f x f x /2 2 f x /2 6 f x /2 3 ti00/to0/p70 prescaler mode register 0 (prm0) 2 prm01 prm00 crc02 16-bit capture/compare register 01 (cr01) coincidence coincidence 16-bit timer register (tm0) clear noise elimi- nation circuit crc02 crc01 crc00 inttm00 to0/ti00/ p70 inttm01 timer output control register (toc0) 16-bit timer mode control register (tmc0) internal bus tmc03 tmc02 tmc01 ovf0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 selector 16-bit capture/compare register 0 (cr00) selector selector selector noise elimi- nation circuit noise elimi- nation circuit output control circuit (1) interval timer tm0 generates interrupt request at the preset time interval. (2) ppg output tm0 can output a square wave whose frequency and output pulse can be set freely. (3) pulse width measurement tm0 can measure the pulse width of an externally input signal. (4) external event counter tm0 can measure the number of pulses of an externally input signal. (5) square-wave output tm0 can output a square wave with any selected frequency. (6) one-shot pulse output tm0 is able to output one-shot pulse which can set any width of output pulse.
160 chapter 8 16-bit timer/event counter 8.3 16-bit timer/event counter configuration 16-bit timer/event counter consists of the following hardware. table 8-2. 16-bit timer/event counter configuration item configuration timer register 16 bits 1 (tm0) register capture/compare register: 16 bits 2 (cr00, cr01) timer output 1 (to0) control register 16-bit timer mode control register (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register (toc0) prescaler mode register 0 (prm0) port mode register 7 (pm7) note note see figure 6-14 p70 to p75 configurations. (1) 16-bit timer register (tm0) tm0 is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of an input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases: <1> at reset input <2> if tmc03 and tmc02 are cleared <3> if valid edge of ti00 is input in the clear & start mode by inputting valid edge of ti00 <4> if tm0 and cr00 coincide with each other in the clear & start mode on coincidence between tm0 and cr00 <5> if ospt is set or if the valid edge of ti00 is input in the one-shot pulse output mode
161 chapter 8 16-bit timer/event counter (2) capture/compare register 00(cr00) cr00 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc00) of capture/compare control register 0. ? when cr00 is used as a compare register the value set in the cr00 is constantly compared with the 16-bit timer register (tm0) count value, and an interrupt request (inttm00) is generated if they match. it can also be used as the register which holds the interval time then tm0 is set to interval timer operation, and as the register which sets the pulse width in the pwm operating mode. ? when cr00 is used as a capture register it is possible to select the valid edge of the ti00/to0/p70 pin or the ti01/p71 pin as the capture trigger. setting of the ti00 or ti01 valid edge is performed by means of prescaler mode register 0 (prm0). if cr00 is specified as a capture register and capture trigger is specified to be the valid edge of the ti00/to0/ p70 pin, the situation is as shown in table 8-3. on the other hand, when capture trigger is specified to be the valid edge of the ti01/p71 pin, the situation is as shown in table 8-4. table 8-3. ti00/to0/p70 pin valid edge and capture/compare register capture trigger es01 es00 ti00/to0/p70 pin valid edge cr00 capture trigger 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation table 8-4. ti01/p71 pin valid edge and capture/compare register capture trigger es11 es10 ti01/p71 pin valid edge cr00 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges cr00 is set by a 16-bit memory manipulation instruction. after reset input, the value of cr00 is undefined. cautions 1. set a value other than 0000h in cr00. this means 1-pulse count operation cannot be performed when cr00 is used as an event counter. however, in the free-running mode and in the clear mode using the valid edge of ti00, if 0000h is set to cr00, an interrupt request (inttm00) is generated following overflow (ffffh). 2. when p70 is used as the valid edge of ti00, it cannot be used as timer output (to0). moreover, when p70 is used as to0, it cannot be used as the valid edge of ti00.
162 chapter 8 16-bit timer/event counter (3) capture/compare register 01 (cr01) cr01 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc02) of capture/compare control register 0. ? when cr01 is used as a compare register the value set in the cr01 is constantly compared with the 16- bit timer register (tm0) count value, and an interrupt request (inttm01) is generated if they match. ? when cr01 is used as a capture register it is possible to select the valid edge of the ti00/to0/p70 pin as the capture trigger. the ti00/to0/p70 valid edge is set by means of prescaler mode register 0 (prm0). cr01 is set with a 16-bit memory manipulation instruction. after reset input, the value of cr01 is undefined. caution set other than 0000h to cr01. this means 1-pulse count operation cannot be performed when cr01 is used as the event counter. however, in the free-running mode and in the clear mode using the valid edge of ti01, if 0000h is set to cr01, an interrupt request (inttm01) is generated following overflow (ffffh). 8.4 registers to control 16-bit timer/event counter the following five types of registers are used to control the 16-bit timer/event counter. ? 16-bit timer mode control register (tmc0) ? capture/compare control register (crc0) ? 16-bit timer output control register 0 (toc0) ? prescaler mode register 0 (prm0) ? port mode register 7 (pm7) (1) 16-bit timer mode control register (tmc0) this register sets the 16-bit timer operating mode, the 16-bit timer register clear mode, and output timing, and detects an overflow. tmc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc0 value to 00h. caution the 16-bit timer register starts operation at the moment a value other than 0, 0 (operation stop mode) is set in tmc02 to tmc03, respectively. set 0, 0 in tmc02 to tmc03 to stop the operation.
163 chapter 8 16-bit timer/event counter figure 8-2. 16-bit timer mode control register (tmc0) format tmc03 tmc02 tmc01 operating mode to0 output timing selection interrupt request generation and clear mode selection 0 0 0 operation stop no change not generated 0 0 1 (tm0 cleared to 0) 0 1 0 free running mode match between tm0 and cr00 or match between tm0 and cr01 0 1 1 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge 1 0 0 clear & start on ti00 valid 101 edge 1 1 0 clear & start on match match between tm0 and between tm0 and cr00 cr00 or match between tm0 and cr01 1 1 1 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge ovf0 16-bit timer register overflow detection 0 overflow not detected 1 overflow detected cautions 1. timer operation must be stopped before writing to bits other than the ovf0 flag. 2. set the valid edge of the ti00/to0/p70 pin with prescaler mode register 0 (prm0). 3. if clear & start mode on match between tm0 and cr00 is selected, when the set value of cr00 is ffffh and the tm0 value changes from ffffh to 0000h, ovf0 flag is set to 1. remarks 1. to0 : 16-bit timer/event counter output pin 2. ti00 : 16-bit timer/event counter input pin 3. tm0 : 16-bit timer register 4. cr00 : compare register 00 5. cr01 : compare register 01 generated on match between tm0 and cr00, or match between tm0 and cr01 7 0 6 0 5 0 4 0 3 tmc03 2 tmc02 1 tmc01 0 ovf0 symbol tmc0 address ff60h after reset: 00h r/w
164 chapter 8 16-bit timer/event counter (2) capture/compare control register 0 (crc0) this register controls the operation of the capture/compare registers (cr00, cr01). crc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets crc0 value to 04h. figure 8-3. capture/compare control register 0 (crc0) format address: ff62h after reset: 04h r/w symbol 76543210 crc0 00000 crc02 crc01 crc00 crc02 cr01 operating mode selection 0 operates as compare register 1 operates as capture register crc01 cr00 capture trigger selection 0 captures on valid edge of ti01n 1 captures on valid edge of ti00n by reverse phase crc00 cr00n operating mode selection 0 operates as compare register 1 operates as capture register cautions 1. timer operation must be stopped before setting crc0. 2. when clear & start mode on a match between tm0 and cr00 is selected with the 16-bit timer mode control register (tmc0), cr00 should not be specified as a capture register. 3. if both the rising and falling edges have been selected as the valid edges of ti00, capture is not performed.
165 chapter 8 16-bit timer/event counter (3) 16-bit timer output control register (toc0) this register controls the operation of the 16-bit timer/event counter output control circuit. it sets r-s type flip- flop (lv0) setting/resetting, output inversion enabling/disabling, 16-bit timer/event counter timer output enabling/ disabling, one-shot pulse output operation enabling/disabling, and output trigger for a one-shot pulse by software. toc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets toc0 value to 00h. figure 8-4 shows the toc0 format. figure 8-4. 16-bit timer output control register l (toc0) format address: ff63h after reset: 00h r/w symbol 7 6 5 43210 toc0 0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 ospt control of one-shot pulse output trigger by software 0 one-shot pulse trigger not used 1 one-shot pulse trigger used ospe one-shot pulse output control 0 continuous pulse output 1 one-shot pulse output note toc04 timer output f/f control by match of cr01 and tm0 0 inversion operation disabled 1 inversion operation enabled lvs0 lvr0 16-bit timer/event counter timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc01 timer output f/f control by match of cr00 and tm0 0 inversion operation disabled 1 inversion operation enabled toe0 16-bit timer/event counter output control 0 output disabled (output set to level 0) 1 output enabled note one-shot pulse output operates normally only in the free-running mode. cautions 1. timer operation must be stopped before setting toc0. 2. if lvs0 and lvr0 are read after data is set, they will be 0. 3. ospt is cleared automatically after data setting, and will therefore be 0 if read.
166 chapter 8 16-bit timer/event counter (4) prescaler mode register 0 (prm0) this register is used to set 16-bit timer (tm0) count clock and ti00, ti01 input valid edges. prm0 is set with an 8-bit memory manipulation instruction. reset input sets prm0 value to 00h. figure 8-5. prescaler mode register 0 (prm0) format address: ff61h after reset: 00h r/w symbol 76543210 prm0 es11 es10 es01 es00 0 0 prm01 prm00 es11 es10 ti01 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es01 es00 ti00 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm01 prm00 count clock selection 00f x (8.38 mhz) 01f x /2 2 (2.09 mhz) 10f x /2 6 (131 khz) 1 1 ti00 valid edge cautions 1. if the valid edge of ti00 is to be set to the count clock, do not set the clear/start mode and the capture trigger at the valid edge of ti00. moreover, do not use the p70/ti00/to0 pins as timer outputs (to0). 2. always set data to prm0 after stopping the timer operation. 3. if the ti00 or ti01 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti00 pin or ti01 pin to enable the operation of the 16-bit timer (tm0). please be careful when pulling up the ti00 pin or the ti01 pin. however, when re-enabling operation after the operation has been stopped once, the rising edge is not detected. remarks 1. f x : main system clock oscillation frequency 2. ti00, ti01: 16-bit timer/event counter input pin 3. figures in parentheses are for operation with f x = 8.38 mhz.
167 chapter 8 16-bit timer/event counter (5) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p70/to0/ti00 pin for timer output, set pm70 and the output latch of p70 to 0. pm7 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 value to ffh. figure 8-6. port mode register 7 (pm7) format 7 1 6 1 5 pm75 4 pm74 3 pm73 2 pm72 1 pm71 0 pm70 symbol pm7 address: ff27h after reset: ffh r/w pm7n 0 1 p7n pin input/output mode selection (n = 0 to 5) output mode (output buffer on) input mode (output buffer off)
168 chapter 8 16-bit timer/event counter 8.5 16-bit timer/event counter operations 8.5.1 interval timer operations setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-7 allows operation as an interval timer. interrupt request is generated repeatedly using the count value set in 16-bit capture/compare register 00 (cr00) beforehand as the interval. when the count value of the 16-bit timer register (tm0) matches the value set to cr00, counting continues with the tm0 value cleared to 0 and the interrupt request signal (inttm00) is generated. count clock of the 16-bit timer/event counter can be selected with bits 0 to 1 (prm00, prm01) of the prescaler mode register 0 (prm0). see 8.6 16-bit timer/event counter operating precautions (2) 16-bit compare-register setting about the operation when the compare register value is changed during timer count operation. figure 8-7. control register settings for interval timer operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare re g ister remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see figures 8-2 and 8-3.
169 chapter 8 16-bit timer/event counter figure 8-8. interval timer configuration diagram 16-bit capture/compare register 00 (cr00) 16-bit timer register (tm0) ovf0 clear circuit inttm00 f x f x /2 2 f x /2 6 ti01/p71 selector figure 8-9. timing of interval timer operation count clock t tm0 count value cr00 inttm00 t00 0000h 0001h n 0000 0001h n 0000h 0001h n n n n n count start clear clear interrupt accepted interrupt accepted interval time interval time interval time remark interval time = (n + 1) t: n = 00h to ffh
170 chapter 8 16-bit timer/event counter 8.5.2 ppg output operations setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-10 allows operation as ppg (programmable pulse generator) output. in the ppg output operation, square waves are output from the to0/ti00/p70 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit capture/compare register 01 (cr01) and in 16- bit capture/compare register 00 (cr00), respectively. figure 8-10. control register settings for ppg output operation (a) 16-bit timer mode control register (tmc0) 0000 tmc03 1 tmc02 1 tmc01 0 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. (b) capture/compare control register 0 (crc0) 00000 crc02 0 crc01 crc00 0 crc0 cr00 as compare register cr01 as compare register (c) 16-bit timer output control register (toc0) 0 ospt 0 ospe 0 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output reverses output on coincidence between tm0 and cr00 specifies initial value of to0 output f/f reverse output on coincidence between tm0 and cr01 disables one-shot pulse output cautions 1. values in the following range should be set in cr00 and cr01: 0000h < cr01 < cr00 ffffh 2. the cycle of the pulse generated through ppg output (cr00 setting value + 1) has a duty of (cr01 setting value + 1)/(cr00 setting value + 1). remark : don't care
171 chapter 8 16-bit timer/event counter 8.5.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00/to0/p70 pin and ti01/p71 pin using the 16-bit timer register (tm0). there are two measurement methods: measuring with tm0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti00/to0/p70 pin. (1) pulse width measurement with free-running counter and one capture register when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-11), and the edge specified by prescaler mode register 0 (prm0) is input to the ti00/to0/p70 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (inttm01) is set. any of three edge can be selectedrising, falling, or both edgesspecified by means of bits 6 and 7 (es10 and es11) of prm0. for valid edge detection, sampling is performed at the count clock selected by prm0), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 8-11. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figures 8-2 and 8-3.
172 chapter 8 16-bit timer/event counter figure 8-12. configuration diagram for pulse width measurement by free-running counter f x f x /2 2 f x /2 6 ti00/to0/p70 16-bit timer register (tm0) ovf0 16-bit capture/compare register (cr01) internal bus inttm01 selector figure 8-13. timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 count clock tm0 count value ti00 pin input cr01 capture value inttm01 ovf0 (d1 ?d0) t (d3 ?d2) t (10000h ?d1 + d2) t d1 d2 d3 d2 d3 d0 + 1 d1 d1 + 1
173 chapter 8 16-bit timer/event counter (2) measurement of two pulse widths with free-running counter when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-14 ), it is possible to simultaneously measure the pulse widths of the two signals input to the ti00/to0/p70 pin and the ti01/p71 pin. when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00/to0/p70 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (inttm01) is set. also, when the edge specified by bits 6 and 7 (es10 and es11) of prm0 is input to the ti01/p71 pin, the value of tm0 is taken into 16-bit capture/compare register 00 (cr00) and an external interrupt request signal (inttm00) is set. any of three edge can be selectedrising, falling, or both edgesas the valid edges for the ti00/to0/p70 pin and the ti01/p71 pin specified by means of bits 4 and 5 (es00 and es01) and bits 6 and 7 (es10 and es11) of intm0, respectively. for ti00/to0/p70 pin valid edge detection, sampling is performed at the interval selected by means of the prescaler mode register 0 (prm0), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 8-14. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 0 crc00 1 crc0 cr00 as capture register captures valid edge of ti01/p71 pin to cr00 cr01 as capture register remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, see figures 8-2 and 8-3.
174 chapter 8 16-bit timer/event counter ? capture operation (free-running mode) capture register operation in capture trigger input is shown. figure 8-15. capture operation with rising edge specified count clock tm0 ti00 rising edge detection cr01 inttm01 n? n? n? n n+1 n figure 8-16. timing of pulse width measurement operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 ti01 pin input cr00 capture value inttm01 inttm00 ovf0 (d1 ?d0) t (d3 ?d2) t (10000h ?d1 + d2) t (10000h ?d1 + (d2 + 1)) t d1 d2 + 1 d1 d2 d2 d3 d0 + 1 d1 d1 + 1 d2 + 1 d2 + 2 count clock tm0 count value ti00 pin input cr01 capture value
175 chapter 8 16-bit timer/event counter (3) pulse width measurement with free-running counter and two capture registers when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-17 ), it is possible to measure the pulse width of the signal input to the ti00//to0/p70 pin. when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00/to0/p70 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (inttm01) is set. also, on the inverse edge input of that of the capture operation into cr01, the value of tm0 is taken into 16- bit capture/compare register 00 (cr00). either of two edge can be selectedrising or fallingas the valid edges for the ti00/to0/p70 pin specified by means of bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). for ti00/to0/p70 pin valid edge detection, sampling is performed at the interval selected by means of the prescaler mode register (prm0), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00/to0/p70 is specified to be both rising and falling edge, capture/compare register 00 (cr00) cannot perform the capture operation. figure 8-17. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 as capture register captures to cr00 at edge reverse to valid edge of ti00/to0/p70. cr01 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details.
176 chapter 8 16-bit timer/event counter figure 8-18. timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 inttm01 ovf0 d2 d1 d3 d2 d3 d0 + 1 d2 + 1 d1 d1 + 1 cr00 capture value count clock tm0 count value ti00 pin input cr01 capture value (d1 ?d0) t (d3 ?d2) t (10000h ?d1 + d2) t (4) pulse width measurement by means of restart when input of a valid edge to the ti00/to0/p70 pin is detected, the count value of the 16-bit timer register (tm0) is taken into 16-bit capture/compare register 01 (cr01), and then the pulse width of the signal input to the ti00/ to0/p70 pin is measured by clearing tm0 and restarting the count (see register settings in figure 8-19). the edge specification can be selected from two types, rising and falling edges by bits 4 and 5 (es00 and es01) of the prescaler mode resister 0 (prm0) in a valid edge detection, the sampling is performed by a cycle selected by the prescaler mode resistor 0 (prm0) and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00/to0/p70 is specified to be both rising and falling edges, the 16-bit capture/compare register 00 (cr00) cannot perform the capture operation.
177 chapter 8 16-bit timer/event counter figure 8-19. control register settings for pulse width measurement by means of restart (a) 16-bit timer mode control register (tmc0) 0000 tmc03 1 tmc02 0 tmc01 0/1 ovf0 0 tmc0 clears and starts at valid edge of ti00/to0/p70 pin. (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 as capture register captures to cr00 at edge reverse to valid edge of ti00/to0/p70. cr01 as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figures 8-2 and 8-3. figure 8-20. timing of pulse width measurement operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm01 d1 t d2 t d2 d1 d2 d1 cr00 capture value count clock tm0 count value ti00 pin input cr01 capture value
178 chapter 8 16-bit timer/event counter 8.5.4 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti00/to0/p70 pin with the 16-bit timer register (tm0). tm0 is incremented each time the valid edge specified with the prescaler mode register 0 (prm0) is input. when the tm0 counted value matches the 16-bit capture/compare register 00 (cr00) value, tm0 is cleared to 0 and the interrupt request signal (inttm00) is generated. input the value except 0000h to cr00. (count operation with a pulse cannot be carried out.) the rising edge, the falling edge, or both edges can be selected with bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). because operation is carried out only after the valid edge is detected twice by sampling at the interval selected with the prescaler mode register 0 (prm0), noise with short pulse widths can be removed. caution when used as an external event counter, the p70/ti00/to0 pin cannot be used as timer output (to0). figure 8-21. control register settings in external event counter mode (a) 16-bit timer mode control register (tmc0) 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. (b) capture/compare control register 0 (crc0) 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see figures 8-2 and 8-3.
179 chapter 8 16-bit timer/event counter figure 8-22. external event counter configuration diagram 16-bit capture/compare register (cr00) internal bus coincidence clear ovf0 inttm00 f x /2 2 f x /2 6 f x noise elimination circuit f x /2 3 valid edge of ti00 16-bit timer/counter (tm0) 16-bit capture/compare register (cr01) selector figure 8-23. external event counter operation timings (with rising edge specified) ti00 pin input tm0 count value cr00 inttm00 0000h 0001h 0002h 0003h 0004h 0005h n? n 0000h 0001h 0002h 0003h n caution when reading the external event counter count value, tm0 should be read. 8.5.5 square-wave output operation a square wave with any selected frequency to be output at intervals of the count value preset to the 16-bit capture/ compare register 00 (cr00) operates. the to0 pin output status is reversed at intervals of the count value preset to cr00 by setting bit 0 (toe0) and bit 1 (toc01) of the 16-bit timer output control register toc0 to 1. this enables a square wave with any selected frequency to be output.
180 chapter 8 16-bit timer/event counter figure 8-24. control register settings in square-wave output mode (a) 16-bit timer mode control register (tmc0) 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. (b) capture/compare control register 0 (crc0) 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare re g ister (c) 16-bit timer output control register (toc0) 0 ospt 0 ospe 0 toc04 0 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output. reverses output on coincidence between tm0 and cr00. specifies initial value of to0 output f/f. does not reverse output on coincidence between tm0 and cr01. disables one-shot pulse output. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see figures 8-2, 8-3, and 8-4.
181 chapter 8 16-bit timer/event counter figure 8-25. square-wave output operation timing count clock tm0 count value cr00 inttm00 to0 pin output 0000h 0001h 0002h n? n 0000h 0001h 0002h n? n 0000h n 8.5.6 one-shot pulse output operation it is possible to output one-shot pulses by software trigger. if the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16-bit timer output control register (toc0) are set as shown in figure 8-26, and 1 is set in bit 6 (ospt) of toc0 by software, a one-shot pulse is output from the to0/ti00/p70 pin. by setting 1 in ospt, the 16-bit timer/event counter is cleared and started, and output is activated by the count value set beforehand in 16-bit capture/compare register 01 (cr01). thereafter, output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (cr00). tm0 continues to operate after one-shot pulse is output. to stop tm0, 00h must be set to tmc0. caution when outputting one-shot pulse, do not set 1 in ospt. when outputting one-shot pulse again, do so after the inttm00, or interrupt match signal with cr00, is generated.
182 chapter 8 16-bit timer/event counter figure 8-26. control register settings for one-shot pulse output operation using software trigger (a) 16-bit timer mode control register (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) 00000 crc02 0 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as compare re g ister (c) 16-bit timer output control register (toc0) 0 ospt 0 ospe 1 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output. reverses output on coincidence between tm0 and cr00. specifies initial value of to0 output f/f. reverses output on coincidence between tm0 and cr01. sets one-shot pulse output mode. set to 1 for output. caution values in the following range should be set in cr00 and cr01. 0000h < cr01 < cr00 ffffh remark 0/1: setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. see figures 8-2, 8-3, and 8-4.
183 chapter 8 16-bit timer/event counter figure 8-27. timing of one-shot pulse output operation using software trigger caution the 16-bit timer register starts operation at the moment a value other than 0, 0 (operation stop mode) is set to tmc02 and tmc03, respectively. sets 0ch to tmc0 (tm0 count starts) count clock tm0 count value cr01 set value cr00 set value ospt inttm01 inttm00 to0 pin output 0000h 0001h n n+1 0000h n? n m? m 0000h 0001h n m n m n m n m
184 chapter 8 16-bit timer/event counter 8.6 16-bit timer/event counter operating precautions (1) timer start errors an error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. this is because the 16-bit timer register (tm0) is started asynchronously with the count pulse. figure 8-28. 16-bit timer register start timing tm0 count value 0000h 0001h 0002h 0004h count pulse timer start 0003h (2) 16-bit compare register setting set other than 0000h to 16-bit capture/compare registers 00, 01 (cr00, cr01). this means 1-pulse count operation cannot be performed when it is used as the event counter. (3) operation after compare register change during timer count operation if the value after the 16-bit capture/compare register 00 (cr00) is changed is smaller than that of the 16-bit timer register (tm0), tm0 continues counting, overflows and then restarts counting from 0. thus, if the value (m) after cr00 change is smaller than that (n) before change, it is necessary to restart the timer after changing cr00. figure 8-29. timings after change of compare register during timer count operation cr00 nm count pulse tm0 count value x? x ffffh 0000h 0001h 0002h remark n > x > m
185 chapter 8 16-bit timer/event counter (4) capture register data retention timings if the valid edge of the ti00/to0/p70 pin is input during 16-bit capture/compare register 01 (cr01) read, cr01 holds data without carrying out capture operation. however, the interrupt request flag (tmif01) is set upon detection of the valid edge. figure 8-30. capture register data retention timing count pulse tm0 count edge input interrupt request flag capture read signal cr01 interrupt value n n+1 n+2 m m+1 m+2 x n+1 capture (5) valid edge setting set the valid edge of the ti00/to0/p70 pin after setting bits 2 and 3 (tmc02 and tmc03) of the 16-bit timer mode control register to 0, 0, respectively, and then stopping timer operation. valid edge is set with bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0). (6) re-trigger of one-shot pulse when outputting one-shot pulse, do not set 1 in ospt. when outputting one-shot pulse again, output it after the inttm00, or interrupt request match signal with cr00, is generated.
186 chapter 8 16-bit timer/event counter (7) operation of ovf0 flag <1> ofv0 flag is set to 1 in the following case. the clear & start mode on match between tm0 and cr00 is selected. ? cr00 is set to ffffh. ? when tm0 is counted up from ffffh to 0000h. figure 8-31. operation timing of ovf0 flag count pulse cr00 tm0 ovf0 inttm00 ffffh fffeh ffffh 0000h 0001h <2> even if the ovf0 flag is cleared before the next count clock (before tm0 becomes 0001h) after the occurrence of tm0 overflow, the ovf0 flag is reset newly and clear is disabled. (8) contending operations (a) the contending operation between the read time of 16-bit capture/compare register (cr00/cr01) and capture trigger input (cr00/cr01 used as capture/register) capture/trigger input is prior to the other. the data read from cr00/cr01 is not defined. (b) the coincidence timing of contending operation between the write period of 16-bit capture/compare register (cr00/cr01) and 16-bit timer register (tm0) (cr00/cr01 used as a compare register) the coincidence discriminant is not performed normally. do not write any data to cr00/cr01 near the coincidence timing. (9) timer operation <1> even if the 16-bit timer register (tm0) is read, the value is not captured by 16-bit capture/compare register 01 (cr01). <2> regardless of the cpus operation mode, when the timer stops, the external interrupt request input noise is not eliminated. <3> one-shot pulse output operates normally only the free-running mode. in the clear & start mode by tm0 and cr00 match , no overflow occurs, and therefore one-shot pulse output is not possible. (10) capture operation if ti00 is specified as the valid edge of the count clock, capture operation by the capture register specified as the trigger for ti00 is not possible.
187 chapter 8 16-bit timer/event counter (11) compare operation <1> when the 16-bit capture/compare register (cr00/cr01) is overwritten during timer operation, match interrupt may be generated or clear operation may not be performed normally if that value is close to the timer value and larger than the timer value. <2> capture operation may not be performed for cr00/cr01 set in compare mode even if a capture trigger has been input. (12) edge detection if the ti00 pin or the ti01 pin is high level immediately after system reset and rising edge or both the rising and falling edges are specified as the valid edge for the ti00 pin or ti01 pin to enable the 16-bit timer (tm0) operation, a rising edge is detected immediately after. be careful when pulling up the ti00 pin or the ti01 pin. however, the rising edge is not detected at restart after the operation has been stopped once.
188 [memo]
189 chapter 9 8-bit timer/event counter 9.1 8-bit timer/event counter functions 8-bit timer/event counter (tm50, tm51) has the following two modes. ? mode using 8-bit timer/event counters alone (individual mode) ? mode using the cascade connection (16-bit resolution: cascade connection mode) these two modes are described next. (1) mode using 8-bit timer/event counters alone (individual mode) the timer operates as an 8-bit timer/event counter. it has the following functions. ? interval timer ? external event counter ? square wave output ? pwm output (2) mode using the cascade connection (16-bit resolution: cascade connection mode) the timer operates as a 16-bit timer/event counter by connecting in cascade. it has the following functions. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square wave output with 16-bit resolution figures 9-1 and 9-2 show 8-bit timer/event counter block diagrams.
190 chapter 9 8-bit timer/event counter figure 9-1. 8-bit timer/event counter 50 block diagram internal bus 8-bit compare register 50 (cr50) ti50/to50/p72 f x /2 4 f x /2 6 f x /2 8 f x /2 10 f x f x /2 2 coincidence mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 invert level timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/ti50/p72 selector 8-bit counter 50 (tm50) selector figure 9-2. 8-bit timer/event counter 51 block diagram internal bus ti51/to51/p73 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 coincidence mask circuit ovf clear 3 tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 invert level timer mode control register 51 (tmc51) s r q r inv selector inttm51 to51/ti51/p73 selector selector selector 8-bit compare register 51 (cr51) 8-bit counter 51 (tm51) s f x /2 11
191 chapter 9 8-bit timer/event counter 9.2 8-bit timer/event counter configurations 8-bit timer/event counter consists of the following hardware. table 9-1. 8-bit timer/event counter configurations item configuration timer register 8-bit counter 5n (tm5n) register 8-bit compare register 5n (cr5n) timer output 2 (to5n) control register timer clock select register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 7 (pm7) note note see figure 6-14 p70 to p75 configurations. remark n = 0, 1 (1) 8-bit counter 5n (tm5n: n = 0,1) tm5n is an 8-bit read-only register which counts the count pulses. when count clock starts, a counter is incremented. tm50 and tm51 can be connected in cascade and used as a 16-bit timer. when tm50 and tm51 can be connected in cascade and used as a 16-bit timer, they can be read by a 16-bit memory operation instruction. however, since they are connected by an internal 8-bit bus, tm50 and tm51 are read separately in two times. thus, take read during count change into consideration and compare them in two times reading. when count value is read during operation, count clock input is temporary stopped, and then the count value is read. in the following situations, count value is set to 00h. <1> reset input <2> when tce5n is cleared <3> when tm5n and cr5n match in clear & start mode if this mode was entered upon match of tm5n and cr5n values. caution in cascade connection mode, the count value is reset to 00h when the lowest timer tce5n is cleared. remark n = 0, 1 (2) 8-bit compare register 5n (cr5n: n = 0, 1) when cr5n is used as a compare resistor, the value set in cr5n is constantly compared with the 8-bit counter (tm5n) count value, and an interrupt request (inttm5n) is generated if they match. (except pwm mode). it is possible to rewrite the value of cr5n within 00h to ffh during count operation. when tm50 and tm51 can be connected in cascade and used as a 16-bit timer, cr50 and cr51 operate as the 16-bit compare register. it compares count value with register value, and if the values are matched, interrupt request (inttm50) are generated. inttm51 interrupt request is also generated at this time. thus, when tm50 and tm51 are used as cascade connection, mask inttm51 interrupt request. caution in cascade connection mode, stop the timer operation before setting the data. remark n = 0, 1
192 chapter 9 8-bit timer/event counter 9.3 registers to control 8-bit timer/event counter the following three types of registers are used to control 8-bit timer/event counters. ? timer clock select register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) ? port mode register 7 (pm7) n = 0, 1 (1) timer clock select register 5n (tcl5n: n = 0, 1) this register sets count clocks of 8-bit timer/event counter 5n and the valid edge of ti50, ti51 input. tcl5n is set with an 8-bit memory manipulation instruction. reset input sets to 00h. figure 9-3. timer clock select register 50 (tcl50) format address: ff71h after reset: 00h r/w symbol 76543210 tcl50 00000 tcl502 tcl501 tcl500 tcl502 tcl501 tcl500 count clock selection 0 0 0 ti50 falling edge 0 0 1 ti50 rising edge 010f x (8.38 mhz) 011f x /2 2 (2.09 mhz) 100f x /2 4 (523 khz) 101f x /2 6 (131 khz) 110f x /2 8 (32.7 khz) 111f x /2 10 (8.18 khz) cautions 1. when rewriting tcl50 to other data, stop the timer operation beforehand. 2. set bits 3 to 7 to 0. remarks 1. when cascade connection is used, the settings of tcl5n0 to tcl5n2 (n = 0, 1) are valid only for the lowermost timer. 2. f x : main system clock oscillation frequency 3. figures in parentheses are for operation with f x = 8.38 mhz
193 chapter 9 8-bit timer/event counter figure 9-4. timer clock select register 51 (tcl51) format address: ff79h after reset: 00h r/w symbol 7 6 5 43210 tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 tcl512 tcl511 tcl510 count clock selection 0 0 0 ti51 falling edge 0 0 1 ti51 rising edge 010f x /2 (4.19 mhz) 011f x /2 3 (1.04 mhz) 100f x /2 5 (261 khz) 101f x /2 7 (65.4 khz) 110f x /2 9 (16.3 khz) 111f x /2 11 (4.09 khz) cautions 1. when rewriting tcl51 to other data, stop the timer operation beforehand. 2. set bit 3 to 7 to 0. remarks 1. when cascade connection is used, the settings of tcl5n0 to tcl5n2 (n = 0, 1) are valid only for the lowermost timer. 2. f x : main system clock oscillation frequency 3. figures in parentheses are for operation with f x = 8.38 mhz (2) 8-bit timer mode control register 5n (tmc5n: n = 0, 1) tmc5n is a register which sets up the following six types. <1> 8-bit counter 5n (tm5n) count operation control <2> 8-bit counter 5n (tm5n) operating mode selection <3> single mode/cascade connection mode selection <4> timer output f/f (flip flop) status setting <5> active level selection in timer f/f control or pwm (free-running) mode. <6> timer output control tmc5n is set by a 1-bit memory operating command or 8-bit memory operating command. reset input sets to 00h. figure 9-5 shows the tmc5n format.
194 chapter 9 8-bit timer/event counter figure 9-5 8-bit timer mode control register 5n (tmc5n) format address: ff70h (tmc50) ff78h (tmc51) after reset: 00h r/w symbol 76543210 tmc5n tce5n tmc5n6 0 tmc5n4 lvs5n lvr5n tmc5n1 toe5n tce5n tm5n count operation control 0 after cleaning to 0, count operation disabled (prescaler disabled) 1 count operation start tmc5n6 tm5n operating mode selection 0 clear and start mode by matching between tm5n and cr5n 1 pwm (free-running) mode tmc5n4 single mode/cascade connection mode selection 0 single mode (use the lowest timer) 1 cascade connection mode (connect to lower timer) lvs5n lvr5n timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited tmc5n1 in other modes (tmc5n6 = 0) in pwm mode (tmc5n6 = 1) timer f/f control active level selection 0 inversion operation disabled active high 1 inversion operation enabled active low toe5n timer output control 0 output disabled (port mode) 1 output enabled remarks 1. in pwm mode, pwm output will be inactive because of tce5n = 0. 2. if lvs5n and lvr5n are read after data is set, 0 is read. 3. n = 0, 1
195 chapter 9 8-bit timer/event counter (3) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p72/to50/ti50 and p73/ti51/to51 pins for timer output, set pm72, pm73, and output latches of p72 and p73 to 0. pm7 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 9-6. port mode register 7 (pm7) format address: ff27h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin input/output mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
196 chapter 9 8-bit timer/event counter 9.4 8-bit timer/event counter operations 9.4.1 8-bit interval timer operation the 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 5n (cr5n). when the count values of the 8-bit counter 5n (tm5n) match the values set to cr5n, counting continues with the tm5n values cleared to 0 and the interrupt request signals (inttm5n) are generated. the count clock of the tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of the timer clock select register 5n (tcl5n). see 9.5 8-bit timer/event counter caution (2) operation after compare register change during timer count operation about the operation when the compare register value is changed during timer count operation. [setting] <1> set the registers. ? tcl5n : select count clock. ? cr5n : compare value ? tmc5n : clear and start mode by match of tm5n and cr5n. (tmc5n = 0000 0b = dont care) <2> after tce5n = 1 is set, count operation starts. <3> if the values of tm5n and cr5n match, the timer output flip-flop inverts. also, inttm5n is generated and tm5n is cleared to 00h. <4> inttm5n generates repeatedly at the same interval. set tce5n to 0 to stop count operation. remark n = 0, 1
197 chapter 9 8-bit timer/event counter figure 9-7. interval timer operation timings (1/3) (a) basic operation t count clock tm5n count cr5n tce5n inttm5n to5n start count clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt received interrupt received interval time interval time interval time remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. n = 0, 1
198 chapter 9 8-bit timer/event counter figure 9-7. interval timer operation timings (2/3) (b) when cr5n = 00h t count clock tm5 cr5n tce5n inttm5n to5n interval time 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n to5n 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt received interrupt received n = 0, 1
199 chapter 9 8-bit timer/event counter figure 9-7. interval timer operation timings (3/3) (d) operated by cr5n transition (m < n) count clock tm5 cr5n tce5n inttm5n to5n 00h n n m n ffh 00h m 00h m cr5n transition tm5n overflows since m < n h (e) operated by cr5n transition (m > n) count clock tm5 cr5n tce5n inttm5n to5n nC1 n n 00h 01h n mC1 m 00h 01h m cr5n transition h n = 0, 1
200 chapter 9 8-bit timer/event counter 9.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti5n by the 8-bit counter 5n (tm5n). tm5n is incremented each time the valid edge specified with the timer clock select register 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n counted values match the values of 8-bit compare register 5n (cr5n), tm5n is cleared to 0 and the interrupt request signal (inttm5n) are generated. whenever the tm5n counted value matches the value of cr5n, inttm5n is generated. remark n = 0, 1 figure 9-8. external event counter operation timings (with rising edge specified) ti5n tm5n count cr5n inttm5n 00 01 02 03 04 05 nC1 n 00 01 02 03 n n = 0, 1
201 chapter 9 8-bit timer/event counter 9.4.3. square-wave output (8-bit resolution) operation a square wave with any selected frequency is output at intervals of the value preset to the 8-bit compare register 5n (cr5n). to5n pin output status is reversed at intervals of the count value preset to cr5n by setting bit 0 (toe5n) of 8- bit timer mode control register 5n (tmc5n) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). [setting] <1> set each register ? set port latch and port mode register to 0. ? tcl5n: select count clock ? cr5n: compared value ? tmc5n: clear and start mode by match of tm5n and cr5n lvs5n lvr5n timer output f/f status setting 1 0 high-level output 0 1 low-level output timer output f/f reverse enable timer output enable ? toe5n = 1 <2> after tce5n=1 is set, count operation starts <3> timer output f/f is reversed by match of tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h <4> timer output f/f is reversed at the same interval and square wave is output from to5n remark n = 0,1 figure 9-9. square-wave output operation timing count clock tmn count value cr5n to5n note count start 00h 01h 02h n? n 00h 01h 02h n? n 00h n note to5n output initial value can be set by bits 2 and 3 (lvr5n, lvs5n) of the 8-bit timer mode control register 5n (tmc5n) remark n = 0,1
202 chapter 9 8-bit timer/event counter 9.4.4 8-bit pwm output operation 8-bit timer/event counter operates as pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty rate pulse determined by the value set to 8-bit compare register 5n (cr5n). set the active level width of pwm pulse to cr5n, and the active level can be selected with bit 1 of tmc5n (tmc5n1). count clock can be selected with bit 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). enable/disable for pwm output can be selected with bit 0 of tmc5n (toe5n). caution rewrite of cr5n in pwm mode is allowed only once in a cycle. remark n = 0, 1 (1) pwm output basic operation [setting] <1> set port latch (p72, 73) and port mode register 7 (pm72, pm73) to 0. <2> set active level width with 8-bit compare register (cr5n). <3> select count clock with timer clock select register 5n (tcl5n). <4> set active level with bit 1 of tmc5n (tmc5n1). <5> count operation starts when bit 7 of tmc5n is set to 1. set tce5n to 0 to stop count operation. [pwm output operation] <1> pwm output (output from to5n) outputs inactive level after count operation starts until overflow is generated. <2> when overflow is generated, the active level set in <1> of setting is output. the active level is output until cr5n matches the count value of 8-bit counter 5n (tm5n). <3> after the cr5n matches the count value, pwm output outputs the inactive level again until overflow is generated. <4> operations <2> and <3> are repeated until the count operation stops. <5> when the count operation is stopped with tce5n = 0, pwm output comes to inactive level. remark n = 0, 1
203 chapter 9 8-bit timer/event counter figure 9-10. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h n active level active level inactive level (b) cr5n = 0 count clock tm5n cr5n tce5n inttm5n to5n l inactive level inactive level 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h 00h n+2 (c) cr5n = ffh n = 0, 1 tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h ffh n+2 inactive level active level inactive level active level inactive level
204 chapter 9 8-bit timer/event counter (2) operated by cr5n transition figure 9-11. timing of operation by change of cr5n (a) cr5n value transits from n to m before overflow of tm5n count clock tm5n cr5n tce5n inttm5n to5n cr5n transition (n ? m) n n+1 n+2 ffh 00h 01h m m+1 m+2 ffh 00h 01h 02h m m+1 m+2 n 02h m h (b) cr5n value transits from n to m after overflow of tm5n count clock tm5n cr5n tce5n inttm5n to5n n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h 03h m m m+1 m+2 cr5n transition (n ? m) (c) cr5n value transits from n to m between two clocks (00h and 01h) after overflow of tm5n count clock tm5n cr5n tce5n inttm5n to5n n n+1 n+2 ffh 00h 01h n n+1 n+2 ffh 00h 01h 02h n 02h n h m m m+1 m+2 cr5n transition (n ? m) n = 0, 1
205 chapter 9 8-bit timer/event counter 9.4.5 interval timer (16-bit) operations when 1 is set in bit 4 (tmc514) of 8-bit timer mode control register 51 (tm51), the 16-bit resolution timer/counter mode is entered. the 8-bit timer/event counter operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit compare registers (cr50, cr51). [setting] <1> set each register tcl50 : select count clock in tm50. cascade-connected tm51 need not be selected. cr50, cr51 : compared value (each value can be set at 00h-ffh) tmc50, tmc51 : select the clear & start mode by match of tm50 and cr50 (tm51 and cr51). tm50 ? tmc50 = 0000 0b : dont care tm51 ? tmc51 = 0001 0b : dont care <2> when tmc51 is set to tce51 = 1 and then, tce50 is set to tce50 = 1, count operation starts. <3> when the values of tm50 and cr50 of cascade-connected timer match, inttm50 of tm50 is generated. (tm50 and tm51 are cleared to 00h) <4> inttm5n generates repeatedly at the same interval. cautions 1. stop timer operation without fail before setting compare register (cr50, cr51). 2. inttm51 of tm51 is generated when tm51 count value matches cr51, even if cascade connection is used. ensure to mask tm51 to prohibit interrupt. 3. set tce50 and tce51 in a sequential order of tm51 and tm50. 4. count restart/stop can only be controlled by setting tce50 of tm50 to 1/0. figure 9-12 shows an example of 16-bit resolution cascade connection mode timing.
206 chapter 9 8-bit timer/event counter figure 9-12. 16-bit resolution cascade connection mode count clock tm50 tm51 cr50 cr51 tce50 tce51 inttm50 to50 operation permit count start interval time 00h 01h n n+1 ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h 00h 01h 02h mC1 m 00h b 00h n m interrupt request generation level reverse counter clear operation stop 9.5 8-bit timer/event counter cautions (1) timer start errors an error with the maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. this is because the 8-bit counter 5n (tm5n) is started asynchronously with the count pulse. figure 9-13. 8-bit counter start timing count pulse tm5n count 00h 01h 02h 03h 04h timer start n = 0, 1
207 chapter 9 8-bit timer/event counter (2) operation after compare register transition during timer count operation if the values after the 8-bit compare register 5n (cr5n) is transmitted is smaller than the value of 8-bit counter 5n (tm5n), tm5n continues counting, overflows and then restarts counting from 0. thus, if the value (m) after cr5n is smaller than value (n) before transition, it is necessary to restart the timer after transitting cr5n. figure 9-14. timing after compare register transition during timer count operation count pulse cr5n tm5 count value nm xC1 x ffh 00h 01h 02h caution except when the ti5n input is selected, always set tce5n = 0 before setting the stop state. remarks 1. n > x > m 2. n = 0, 1 (3) tm5n (n = 0, 1) reading during timer operation when reading tm5n during operation, select count clock having high/low level wave form longer than two cycles of cpu clock because count clock stops temporary. for example, in the case where cpu clock (f cpu ) is fx, when the selected count clock is fx/4 or below, it can be read. remark n = 0, 1
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209 chapter 10 watch timer 10.1 watch timer functions the watch timer has the following functions. ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. figure 10-1 shows the watch timer block diagram. figure 10-1. watch timer block diagram f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector selector
210 chapter 10 watch timer (1) watch timer when the main system clock or subsystem clock is used, interrupt requests (intwt) are generated at 0.5 second or 0.25 second intervals. (2) interval timer interrupt requests (intwti) are generated at the preset time interval. table 10-1. interval timer interval time interval time when operated at when operated at when operated at f x = 8.38 mhz f x = 4.19 mhz f xt = 32.768 khz 2 11 1/f x 2 4 1/f xt 244 m s 489 m s 488 m s 2 12 1/f x 2 5 1/f xt 489 m s 978 m s 977 m s 2 13 1/f x 2 6 1/f xt 978 m s 1.96 ms 1.95 ms 2 14 1/f x 2 7 1/f xt 1.96 ms 3.91 ms 3.91 ms 2 15 1/f x 2 8 1/f xt 3.91 ms 7.82 ms 7.81 ms 2 16 1/f x 2 9 1/f xt 7.82 ms 15.6 ms 15.6 ms remark f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 10.2 watch timer configuration the watch timer consists of the following hardware. table 10-2. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
211 chapter 10 watch timer 10.3 register to control watch timer watch timer mode control register (wtm) is a register to control watch timer. ? watch timer mode control register (wtm) this register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. wtm is set with an 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 10-2. watch timer mode control register (wtm) format address: ff41h after reset: 00h r/w symbol 7 6 5 43210 wtm wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm7 watch timer count clock selection 0f x /2 7 (65.4 khz) 1f xt (32.768 khz) wtm6 wtm5 wtm4 prescaler interval time selectionn 0002 4 /f w 0012 5 /f w 0102 6 /f w 0112 7 /f w 1002 8 /f w 1012 9 /f w other than above setting prohibited wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer enables operation 0 operation stop (clear both prescaler and timer) 1 operation enable remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. figures in parentheses apply to operation with f x = 8.38 mhz, f xt = 32.768 khz.
212 chapter 10 watch timer 10.4 watch timer operations 10.4.1 watch timer operation when the 32.768-khz subsystem clock or 8.38-mhz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. the watch timer generates an interrupt request (intwt) at the constant time interval. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer mode control register (wtm) is set to 1, the 5-bit counter is cleared and the count operation stops. for simultaneous operation of the interval timer, zero-second start can be achieved by setting wtm1 to 0. however, an error up to 0.5 seconds may occur in the case of watch timer overflow. 10.4.2 interval timer operation the watch timer operates as interval timer which generates interrupt requests (intwti) repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm4 to wtm6) of the watch timer mode control register (wtm). table 10-3. interval timer interval time wtm6 wtm5 wtm4 interval time when operated at when operated at when operated at f x = 8.38 mhz f x = 4.19 mhz f xt = 32.768 khz 0002 4 1/f w 244 m s 489 m s 488 m s 0012 5 1/f w 489 m s 978 m s 977 m s 0102 6 1/f w 978 m s 1.96 ms 1.95 ms 0112 7 1/f w 1.96 ms 3.91 ms 3.91 ms 1002 8 1/f w 3.91 ms 7.82 ms 7.81 ms 1012 9 1/f w 7.82 ms 15.6 ms 15.6 ms other than above setting prohibited remark f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency
213 chapter 10 watch timer figure 10-3. operation timing of watch timer/interval timer 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.5 s) interval time (t) t interrupt time of watch timer (0.5 s) n x t n x t remark f w : watch timer clock frequency n : the number of times of interval timer operations figures in parentheses are for operation with f w = 32.768 khz
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215 chapter 11 watchdog timer 11.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer ? oscillation stabilization time selection caution select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (wdtm). (the watchdog timer and the interval timer cannot be used simultaneously.) figure 11-1 shows a block diagram of the watchdog timer. figure 11-1. watchdog timer block diagram f x /2 8 run clock input circuit control intwdt reset wdt mode signal 3 osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 run wdtm4 internal bus division circuit divided clock selection circuit output controller devision mode selection circuit wdtm3 oscillation stabilization time select register (osts) watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm)
216 chapter 11 watchdog timer (1) watchdog timer mode a runaway is detected. upon detection of the runaway, a non-maskable interrupt request or reset can be generated. table 11-1. watchdog timer runaway detection times runaway detection times 2 12 1/f x (489 m s) 2 13 1/f x (978 m s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz (2) interval timer mode interrupt requests are generated at the preset time intervals. table 11-2. interval times interval time 2 12 1/f x (489 m s) 2 13 1/f x (978 m s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz
217 chapter 11 watchdog timer 11.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 11-3. watchdog timer configuration item configuration control register watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) oscillation stabilization time select register (osts) 11.3 registers to control the watchdog timer the following three types of registers are used to control the watchdog timer. ? watchdog timer clock select register (wdcs) ? watchdog timer mode register (wdtm) ? oscillation stabilization time select register (osts)
218 chapter 11 watchdog timer (1) watchdog timer clock select register (wdcs) this register sets overflow time of the watchdog timer and the interval timer. wdcs is set by an 8-bit memory manipulation instruction. reset input sets wdcs to 00h. figure 11-2. watchdog timer clock select register (wdcs) format address: ff42h after reset: 00h r/w symbol 76543210 wdcs 00000 wdcs2 wdcs1 wdcs0 wdcs2 wdcs1 wdcs0 overflow time of watchdog timer/interval timer 0002 12 /f x (489 m s) 0012 13 /f x (978 m s) 0102 14 /f x (1.96 ms) 0112 15 /f x (3.91 ms) 1002 16 /f x (7.82 ms) 1012 17 /f x (15.6 ms) 1102 18 /f x (31.3 ms) 1112 20 /f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz
219 chapter 11 watchdog timer (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 11-3. watchdog timer mode register (wdtm) format address: fff9h after reset: 00h r/w symbol 7 6 5 43210 wdtm run 0 0 wdtm4 wdtm3 0 0 0 run watchdog timer operation mode selection note 1 0 count stop 1 counter is cleared and counting starts wdtm4 wdtm3 watchdog timer operation mode selection note 2 0 interval timer mode note 3 (maskable interrupt request occurs upon generation of an overflow) 1 0 watchdog timer mode 1 (non-maskable interrupt request occurs upon generation of an overflow) 1 1 watchdog timer mode 2 (reset operation is activated upon generation of an overflow) notes 1. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. 2. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 3. the watchdog timer starts operations as the interval timer when 1 is set to run. caution when 1 is set to run so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by watchdog timer clock select register (wdcs). remark : dont care
220 chapter 11 watchdog timer (3) oscillation stabilization time select register (osts) a register to select oscillation stabilization time from reset time or stop mode released time to the time when oscillation is stabilized. osts is set by an 8-bit memory operation instruction. by reset input, it is turned into 04h. thus, when releasing the stop mode by reset input, the time required to release is 2 17 /fx. figure 11-4. oscillation stabilization time select register (osts) format address: fffah after reset: 04h r/w symbol 76543210 osts 00000 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time 0002 12 /f x (488 m s) 0012 14 /f x (1.95 ms) 0102 15 /f x (3.91 ms) 0112 16 /f x (7.81 ms) 1002 17 /f x (15.6 ms) other than the above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz
221 chapter 11 watchdog timer 11.4 watchdog timer operations 11.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect any runaway. the runaway detection time interval is selected with bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set runaway time interval. the watchdog timer can be cleared and counting is started by setting run to 1. if run is not set to 1 and the runaway detection time is exceeded, system reset or a non-maskable interrupt request is generated according to wdtm bit 3 (wdtm3) value. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. cautions 1. the actual runaway detection time may be shorter than the set time by a maximum of 0.5%. 2. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 11-4. watchdog timer runaway detection time runaway detection time 2 12 1/f x (489 m s) 2 13 1/f x (978 m s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
222 chapter 11 watchdog timer 11.4.2 interval timer operation the watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 3 (wdtm3) and bit 4 (wdtm4) of the watchdog timer mode register (wdtm) are set to 1 and 0, respectively. the interval time of interval timer is selected with bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). when 1 is set to bit 7 (run) of wdtm, the watchdog timer operates as the interval timer. when the watchdog timer operated as the interval timer, the interrupt mask flag (wdtmk) and priority specify flag (wdtpr) are validated and the maskable interrupt request (intwdt) can be generated. among maskable interrupts, intwdt has the highest priority at default. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set run to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (this selects the watchdog timer mode), the interval timer mode is not set unless reset input is applied. 2. the interval time just after setting by wdtm may be shorter than the set time by a maximum of 0.5%. 3. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 11-5. interval timer interval time interval time 2 12 1/f x (489 m s) 2 13 1/f x (978 m s) 2 14 1/f x (1.96 ms) 2 15 1/f x (3.91 ms) 2 16 1/f x (7.82 ms) 2 17 1/f x (15.6 ms) 2 18 1/f x (31.3 ms) 2 20 1/f x (125 ms) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
223 chapter 12 clock output/buzzer output control circuits 12.1 clock output/buzzer output control circuit functions the clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsis. the clock selected with the clock output selection register (cks) is output. in addition, the buzzer output is intended for square wave output of buzzer frequency selected with cks. figure 12-1 shows the block diagram of clock output/buzzer output control circuits. figure 12-1. clock output/buzzer output control circuit block diagram 8 4 bzoe bcs0, bcs1 clock control circuit cloe buz/p75 pcl/p74 internal bus selector bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 clock output selection register (cks) selector prescaler f x /2 10 to f x /2 13 f x to f x /2 7 f xt f x
224 chapter 12 clock output/buzzer output control circuits 12.2 clock output/buzzer output control circuit configuration the clock output/buzzer output control circuits consists of the following hardware. table 12-1. configuration of clock output/buzzer output control circuits item configuration control register clock output selection register (cks) port mode register (pm7) note note see figure 6-14 p70 to p75 configurations . 12.3 register to control clock output/buzzer output control circuit the following two types of registers are used to control the clock output/buzzer output control circuits. ? clock output selection register (cks) ? port mode register (pm7) (1) clock output selection register (cks) this register sets output enable/disable for clock output (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets cks to 00h.
225 chapter 12 clock output/buzzer output control circuits figure 12-2. clock output selection register (cks) format address: ff40h after reset: 00h r/w symbol 7 6 5 43210 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 stop clock division circuit operation. buz fixed to low level. 1 enable clock division circuit operation. buz output enabled. bcs1 bcs0 buz output clock selection 00f x /2 10 (8.18 khz) 01f x /2 11 (4.09 khz) 10f x /2 12 (2.04 khz) 11f x /2 13 (1.02 khz) cloe pcl output enable/disable setting 0 stop clock division circuit operation. pcl fixed to low level 1 enable clock division circuit operation. pcl output enabled. ccs3 ccs2 ccs1 ccs0 pcl output clock selection 0000f x (8.38 mhz) 0001f x /2 (4.19 mhz) 0010f x /2 2 (2.09 mhz) 0011f x /2 3 (1.04 mhz) 0100f x /2 4 (524 khz) 0101f x /2 5 (262 khz) 0110f x /2 6 (131 khz) 0111f x /2 7 (65.5 khz) 1000f xt (32.768 khz) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. figures in parentheses are for operation with f x = 8.38 mhz.
226 chapter 12 clock output/buzzer output control circuits (2) port mode register (pm7) this register sets port 7 input/output in 1-bit units. when using the p74/pcl pin for clock output and the p75/buz pin for buzzer output, set pm74, pm75 and the output latch of p74, p75 to 0. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 12-3. port mode register 7 (pm7) format address: ff27h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin input/output mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
227 chapter 12 clock output/buzzer output control circuits 12.4 clock output/buzzer output control circuit operations 12.4.1 operation as clock output the clock pulse is output as the following procedure. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the clock output selection register (cks) (clock pulse output in disabled status). <2> set bit 4 (cloe) of cks to 1, and enable clock output. remark the clock output control circuit is designed not to output pulses with a small width during output enable/ disable switching of the clock output. as shown in figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after securing high level of the clock. figure 12-4. remote control output application example cloe clock output ** 12.4.2 operation as buzzer output the buzzer frequency is output as the following procedure. <1> select the buzzer output frequency with bits 5 and 6 (bcs0, bcs1) of the clock output selection register (cks) (buzzer output in disabled status). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output.
228 [memo]
229 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) 13.1 a/d converter functions a/d converter is an 8-bit resolution converter that converts analog inputs into digital values. it can control up to 8 analog input channels (ani0 to ani7). (1) hardware start conversion is started by trigger input (adtrg: rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting the a/d converter mode register (adm0). select one channel for analog input from ani0 to ani7 to perform a/d conversion. in the case of hardware start, a/d conversion stops when an a/d conversion operation ends and an interrupt request (intad0) is generated. in the case of software start, a/d conversion is repeated. each time an a/d conversion operation ends, an interrupt request (intad0) is generated. figure 13-1. 8-bit a/d converter block diagram note the effective edge is specified by bit 3 of the egp and egn registers (see figure 19-5 external interrupt rising edge enable register egp, external interrupt falling edge enable register egn format .) ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 sample & hold circuit voltage comparator successive approximation register (sar) control circuit edge detector adirg/intp3//p03 3 a/d conversion result register (adcr0) av dd av ref av ss intad0 intp3 trigger enable a/d converter mode register (adm0) analog input channel specification register (ads0) internal bus ads02 ads01 ads00 adsc0 trg0 fr02 fr01 fr00 ega01 ega00 selector tap selector edge detector note
230 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) 13.2 a/d converter configuration the a/d converter consists of the following hardware. table 13-1. a/d converter configuration item configuration analog input 8 channels (ani0 to ani7) registers successive approximation register (sar) a/d conversion result register (adcr0) control register a/d converter mode register (adm0) analog input channel specification register (ads0) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare value) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is held (end of a/d conversion), the sar contents are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr0) the adcr0 is an 8-bit register that stores the a/d conversion result. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. adcr0 is read by an 8-bit memory manipulation instruction. reset input sets adcr0 to 00h. caution when writing is performed to the a/d converter mode register (adm0) and analog input channel specification register (ads0), the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0, ads0. using a timing other than the above may cause an incorrect conversion result to be read. (3) sample & hold circuit the sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref and av ss , and generates a voltage to be compared to the analog input.
231 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) (6) ani0 to ani7 pins these are eight analog input pins to input analog signals to undergo a/d conversion to the a/d converter. ani0 to ani7 are alternate-function pins that can also be used for digital input. cautions 1. use ani0 to ani7 input voltages within the specification range. if a voltage higher than av ref or lower than av ss is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. 2. analog input (ani0 to ani7) pins are alternate function pins that can also be used as input port (p10 to p17) pins. when a/d conversion is performed by selecting any one of ani0 through ani7, do not execute any input instruction to port 1 during conversion. it may cause the lower conversion resolution. when a digital pulse is applied to a pin adjacent to the pin in the process of a/d conversion, a/d conversion values may not be obtained as expected due to coupling noise. thus, do not apply any pulse to a pin adjacent to the pin in the process of a/d conversion. (7) av ref pin this pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani7 into digital signals according to the voltage applied between av ref and av ss . caution a series resistor string of approx. 10 k w is connected between the av ref pin and av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in parallel. this may cause a greater reference voltage error. (8) av ss pin this is the gnd potential pin of the a/d converter. always keep it at the same potential as the v ss0 pin even when not using the a/d converter. (9) av dd pin this is the a/d converter analog power supply pin. always keep it at the same potential as the v dd0 pin even when not using the a/d converter.
232 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) 13.3 registers to control a/d converter the following 4 types of registers are used to control the a/d converter. ? a/d converter mode register (adm0) ? analog input channel specification register (ads0) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) (1) a/d converter mode register (adm0) this register sets the conversion time for analog input to be a/d converted, conversion start/stop, and external trigger. adm0 is set by an 8-bit memory manipulation instruction. reset input sets adm0 to 00h.
233 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) figure 13-2. a/d converter mode register (adm0) format address: ff80h after reset: 00h r/w symbol 7 6 5 43210 adm0 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 0 adcs0 a/d conversion operation control 0 stop conversion operation. 1 enable conversion operation. trg0 software start/hardware start selection 0 software start 1 hardware start fr02 fr01 fr00 conversion time selection note 1 0 0 0 144/f x (17.1 m s) 0 0 1 120/f x (14.3 m s) 0 1 0 96/f x (setting prohibited note 2 ) 1 0 0 72/f x (setting prohibited note 2 ) 1 0 1 60/f x (setting prohibited note 2 ) 1 1 0 48/f x (setting prohibited note 2 ) other than above setting prohibited ega01 ega00 external trigger signal, edge specification 0 0 no edge detection 0 1 falling edge detection 1 0 rising edge detection 1 1 both falling and rising edge detection notes 1. set so that the a/d conversion time is 14 m s or more. 2. setting prohibited because a/d conversion time is less than 14 m s. caution when rewriting fr00 to fr02 to other than the same data, stop a/d conversion operations once prior to performing rewrite. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
234 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) (2) analog input channel specification register (ads0) this register specifies the analog voltage input port for a/d conversion. ads0 is set by an 8-bit memory manipulation. reset input sets ads0 to 00h. figure 13-3. analog input channel specification register (ads0) format address: ff81h after reset: 00h r/w symbol 76543210 ads0 00000 ads02 ads01 ads00 ads02 ads01 ads00 analog input channel specification 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 1 0 1 ani5 1 1 0 ani6 1 1 1 ani7
235 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) (3) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp3. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets egp and egn to 00h. figure 13-4. external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) format address: ff48h after reset: 00h r/w symbol 7 6 5 43210 egp 0 0 0 0 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 43210 egn 0 0 0 0 egn3 egn2 eng1 eng0 egpn egnn intpn pin valid edge selection (n = 0 to 3) 0 0 interrupt disable 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges
236 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) 13.4 a/d converter operations 13.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with the analog input channel specification register (ads0). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> bit 7 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <5> the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set. if the analog input is smaller than (1/2) av ref , the msb is reset. <6> next, bit 6 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 7, as described below. ? bit 7 = 1: (3/4) av ref ? bit 7 = 0: (1/4) af ref the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 6 = 1 ? analog input voltage < voltage tap: bit 6 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 8 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in the a/d conversion result register (adcr0). at the same time, the a/d conversion end interrupt request (intad0) can also be generated. caution the first a/d conversion value just after a/d conversion operations start may not fall within the rating.
237 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) figure 13-5. basic operation of 8-bit a/d converter conversion time sampling time sampling a/d conversion undefined 80h c0h or 40h conversion result a/d converter operation sar adcr0 intad0 conversion result a/d conversion operations are performed continuously until bit 7 (adcs0) of the a/d converter mode register (adm0) is reset (0) by software. if a write operation is performed to the adm0 or the analog input channel specification register (ads0) during an a/d conversion operation, the conversion operation is initialized, and if the adcs0 bit is set (1), conversion starts again from the beginning. reset input sets the a/d conversion result register (adcr0) to 00h.
238 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) 13.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (stored in the a/d conversion result register (adcr0)) is shown by the following expression. adcr0 = int ( v in 256 + 0.5) av ref or (adcr0 C 0.5) av ref v in < (adcr0 + 0.5) av ref 256 256 where, int( ) : function which returns integer part of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr0 : a/d conversion result register (adcr0) value figure 13-6 shows the relationship between the analog input voltage and the a/d conversion result. figure 13-6. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av ref
239 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) 13.4.3 a/d converter operation mode one analog input channel is selected from among ani0 to ani7 by the analog input channel specification register (ads0) and start a/d conversion. a/d conversion can be started in either of the following two ways. ? hardware start : conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges enabled). ? software start : conversion is started by specifying the a/d converter mode register (adm0). the a/d conversion result is stored in the a/d conversion result register (adcr0), and the interrupt request signal (intad0) is simultaneously generated. (1) a/d conversion by hardware start when bit 6 (trg0) and bit 7 (adcs0) of the a/d converter mode register (adm0) are set to 1, the a/d conversion standby state is set. when the external trigger signal (adtrg) is input, a/d conversion of the voltage applied to the analog input pins specified by the analog input channel specification register (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is not started until a new external trigger signal is input. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and waits for a new external trigger signal to be input. when the external trigger input signal is reinput, a/d conversion is carried out from the beginning. if ads0 is rewritten during a/d conversion waiting, a/d conversion starts when the following external trigger input signal is input. if data with adcs0 set to 0 is written to adm0 during a/d conversion, a/d conversion stops immediately. caution when p03/intp3/adtrg is used as the external trigger input (adtrg), specify the valid edge by bits 1 and 2 (ega00, ega01) of the a/d converter mode register (adm0) and set the interrupt mask flag (pmk3) to 1.
240 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) figure 13-7. a/d conversion by hardware start (when falling edge is specified) a/d conversion adcr0 adtrg intad0 adm0 set adcs0 = 1, trg0 = 1 standby state anin anin anin anim anim anim anin anin anin anim anim standby state standby state ads0 rewrite remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7
241 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) (2) a/d conversion by software start when bit 6 (trg0) and bit 7 (adcs0) of the a/d converter mode register (adm0) are set to 0 and 1, respectively, a/d conversion of the voltage applied to the analog input pin specified by the analog input channel specification register (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is immediately started. a/d conversion operations are repeated until new data is written to ads0. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and a/d conversion of the newly selected analog input channel is started. if data with adcs0 set to 0 is written to adm0 during a/d conversion operation, the a/d conversion operation stops immediately. figure 13-8. a/d conversion by software start adm0 set adcs0 = 1, trg0 = 0 ads0 rewrite adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion suspended; conversion results are not stored remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7
242 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) 13.5 a/d converter cautions (1) current consumption in standby mode a/d converter stops operating in the standby mode. at this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (adcs0) of the a/d converter mode register (adm0) to 0). figure 13-9 shows how to reduce the current consumption in the standby mode. figure 13-9. example of method of reducing current consumption in standby mode av ref av ss p-ch series resistor string adcs0 (2) input range of ani0 to ani7 the input voltages of ani0 to ani7 should be within the specification range. in particular, if a voltage higher than av ref or lower than av ss is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations <1> contention between a/d conversion result register (adcr0) write and adcr0 read by instruction upon the end of conversion adcr0 read is given priority. after the read operation, the new conversion result is written to adcr0. <2> contention between adcr0 write and external trigger signal input upon the end of conversion the external trigger signal is not accepted during a/d conversion. therefore, the external trigger signal is not accepted during adcr0 write. <3> contention between adcr0 write and a/d converter mode register (adm0) write or analog input channel specification register (ads0) write adm0 or ads0 write is given priority. adcr0 write is not performed, nor is the conversion end interrupt request signal (intad0) generated.
243 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) <4> noise countermeasures to maintain the 8-bit resolution, attention must be paid to noise input to pin av ref and pins ani0 to ani7. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 13-10 to reduce noise. figure 13-10. analog input pin connection reference voltage input c = 100 to 1000pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref v dd0 av dd av ss v ss0 ani0 to ani7 (5) ani0 to ani7 the analog input pins (ani0 to ani7) also function as input/output port pins (p10 to p17). when a/d conversion is performed with any of pins ani0 to ani7 selected, do not execute an input instruction to port 1 while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/ d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) av ref pin input impedance a series resistor string of approx. 10 k w is connected between the av ref pin and the av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in parallel. this may cause a greater reference voltage error.
244 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) (7) interrupt request flag (adif0) the interrupt request flag (adif0) is not cleared even if the analog input channel specification register (ads0) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads0 rewrite. caution is therefore required since, at this time, when adif0 is read immediately just after the ads0 rewrite, adif0 is set despite the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is stopped and then resumed, clear adif0 before the a/d conversion operation is resumed. figure 13-11. a/d conversion end interrupt request generation timing adm0 rewrite (start of anin conversion) a/d conversion adcr0 intad0 anin anin anim anim anin anin anim anim ads0 rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7
245 chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) (8) av dd pin the av dd pin is the analog circuit power supply pin. it supplies power to the input circuits of the ani0 to ani7 pins. therefore, be sure to apply the same voltage as v dd0 to this pin even when the application circuit is designed so as to switch its power supply to a backup battery. figure 13-12. av dd pin connection main power supply capacitor for back-up av ref v dd0 av ss av dd v ss0 (9) conversion results just after a/d conversion start the first a/d conversion value just after a/d conversion operations start may not fall within the rating. polling a/d conversion end interrupt request (intad0) and take measures such as removing the first conversion results. (10) a/d conversion result register (adcr0) read operation when writing is performed to the a/d converter mode register (adm0) and analog input channel specification register (ads0), the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0, ads0. using a timing other than the above may cause an incorrect conversion result to be read.
246 [memo]
247 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) 14.1 a/d converter functions a/d converter is a 10-bit resolution converter that converts analog inputs into digital signals. it can control up to 8 analog input channels (ani0 to ani7). (1) hardware start conversion is started by trigger input (adtrg: rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting the a/d converter mode register (adm0). select one channel for analog input from ani0 to ani7 to start a/d conversion. in the case of hardware start, the a/d converter stops when a/d conversion is completed, and an interrupt request (intad0) is generated. in the case of software start, a/d conversion is repeated. each time as a/d conversion operation ends, an interrupt request (intad0) is generated. figure 14-1. 10-bit a/d converter block diagram note the effective edge is specified by bit 3 of the egp and egn registers (see figure 19-5 external interrupt rising edge enable register egp, external interrupt falling edge enable register egn format .) ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 sample & hold circuit series resistor string voltage comparator control circuit edge detector adtrg/intp3/p03 3 a/d conversion result register (adcr0) av dd av ref av ss intad0 intp3 trigger enable a/d converter mode register (adm0) analog input channel specification register (ads0) internal bus ads02 ads01 ads00 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 selector tap selector edge detector note successive approximation register (sar)
248 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) 14.2 a/d converter configuration a/d converter consists of the following hardware. table 14-1. a/d converter configuration item configuration analog input 8 channels (ani0 to ani7) registers successive approximation register (sar) a/d conversion result register (adcr0) control register a/d converter mode register (adm0) analog input channel specification register (ads0) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare value) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is hold (end of a/d conversion), the sar contents are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr0) this is a 16-bit register which stores the a/d conversion results. lower 6-bit is fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register (sar) and held by this register. adcr0 is read by a 16-bit memory manipulation instruction. reset input sets adcr0 to 00h. caution when writing is performed to the a/d converter mode register (adm0) and analog input channel specification register (ads01), the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0, ads0. using a timing other than the above may cause an incorrect conversion result to be read. (3) sample & hold circuit the sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref and av ss , and generates a voltage to be compared to the analog input.
249 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) (6) ani0 to ani7 pins these are eight analog input pins to input analog signals to undergo a/d conversion to the a/d converter. ani0 to ani7 are dual-function pins that can also be used for digital input. cautions 1. use ani0 to ani7 input voltages within the specification range. if a voltage higher than av ref or lower than av ss is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. 2. analog input (ani0 to ani7) pins are alternate function pins that can also be used as input port (p10 to p17) pins. when a/d conversion is performed by selecting any one of ani0 through ani7, do not execute any input instruction to port1 during conversion. it may cause the lower conversion resolution. when a digital pulse is applied to a pin adjacent to the pin in the process of a/d conversion, a/d conversion values may not be obtained as expected due to coupling noise. thus, do not apply any pulse to a pin adjacent to the pin in the process of a/d conversion. (7) av ref pin this pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani7 into digital signals according to the voltage applied between av ref and av ss . caution a series resistor string of approx. 10 k w is connected between the av ref and av ss pins. therefore, when output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in parallel. this may cause a greater reference voltage error. (8) av ss pin this is the gnd potential pin of the a/d converter. always keep it at the same potential as the v ss0 pin when not using the a/d converter. (9) av dd pin this is the a/d converter analog power supply pin. always keep it at the same potential as the v dd0 pin even when not using the a/d converter. 14.3 registers to control a/d converter the following 4 types of registers are used to control a/d converter. ? a/d converter mode register (adm0) ? analog input channel specification register (ads0) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) (1) a/d converter mode register (adm0) this register sets the conversion time for analog input to be a/d converted, conversion start/stop, and external trigger. adm0 is set by an 8-bit memory manipulation instruction. reset input sets adm0 to 00h.
250 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) figure 14-2. a/d converter mode register (adm0) format address: ff80h after reset: 00h r/w symbol 76543210 adm0 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 0 adcs0 a/d conversion operation control 0 stop conversion operation. 1 enable conversion operation. trg0 software start/hardware start selection 0 software start 1 hardware start fr02 fr01 fr00 conversion time selection note 1 0 0 0 144/f x (17.1 m s) 1 0 1 120/f x (14.3 m s) 0 1 0 96/f x (setting prohibited note 2 ) 1 0 0 72/f x (setting prohibited note 2 ) 1 0 1 60/f x (setting prohibited note 2 ) 1 1 0 48/f x (setting prohibited note 2 ) other than above setting prohibited ega01 ega00 external trigger signal, edge specification 0 0 no edge detection 0 1 falling edge detection 1 0 rising edge detection 1 1 both falling and rising edge detection notes 1. set so that the a/d conversion time is 14 m s or more. 2. setting prohibited because a/d conversion time is less than 14 m s. caution when rewrite fr00 to fr02 to other than the same data, stop a/d conversion operations once before performing it. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz.
251 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) (2) analog input channel specification register (ads0) this register specifies the analog voltage input port for a/d conversion. ads0 is set by an 8-bit memory manipulation. reset input sets ads0 to 00h. figure 14-3. analog input channel specification register (ads0) format address: ff81h after reset: 00h r/w symbol 7 6 5 43210 ads0 0 0 0 0 0 ads02 ads01 ads00 ads02 ads01 ads00 analog input channel specification 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 1 0 1 ani5 1 1 0 ani6 1 1 1 ani7 (3) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp3. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets egp and egn to 00h. figure 14-4. external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) format address: ff48h after reset: 00h r/w symbol 7 6 5 43210 egp 0 0 0 0 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 43210 egn 0 0 0 0 egn3 egn2 eng1 eng0 egpn egnn intpn pin valid edge selection (n = 0 to 3) 0 0 interrupt disable 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges
252 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) 14.4 a/d converter operation 14.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with the analog input channel specification register (ads0). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <5> the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set. if the analog input is smaller than (1/2) av ref , the msb is reset. <6> next, bit 6 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and analog input voltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in the a/d conversion result register (adcr0). at the same time, the a/d conversion end interrupt request (intad0) can also be generated. caution the first a/d conversion value just after a/d conversion operations start may not fall within the rating.
253 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) figure 14-5. basic operation of 10-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr0 intad0 conversion result a/d conversion operations are performed continuously until bit 7 (adcs0) of the a/d converter mode register (adm0) is reset (0) by software. if a write operation is performed to the adm0 or the analog input channel specification register (ads0) during an a/d conversion operation, the conversion operation is initialized, and if the adcs0 bit is set (1), conversion starts again from the beginning. reset input sets the a/d conversion result register (adcr0) to 00h.
254 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) 14.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (stored in the a/d conversion result register (adcr0)) is shown by the following expression. adcr0 = int ( v in 1024 + 0.5) av ref or (adcr0 C 0.5) av ref v in < (adcr0 + 0.5) av ref 1024 1024 where, int( ) : function which returns integer part of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr0: a/d conversion result register (adcr0) value figure 14-6 shows the relationship between the analog input voltage and the a/d conversion result. figure 14-6. relationship between analog input voltage and a/d conversion result 1023 1022 1021 3 2 1 0 a/d conversion result (adcr0) 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 input voltage/av ref
255 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) 14.4.3 a/d converter operation mode select one analog input channel from among ani0 to ani7 by the analog input channel specification register (ads0) to start a/d conversion. a/d conversion can be started in either of the following two ways. ? hardware start : conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges enabled). ? software start : conversion is started by specifying the a/d converter mode register (adm0). the a/d conversion result is stored in the a/d conversion result register (adcr0), and the interrupt request signal (intad0) is simultaneously generated. (1) a/d conversion by hardware start when bit 6 (trg0) and bit 7 (adcs0) of the a/d converter mode register (adm0) are set to 1, the a/d conversion standby state is set. when the external trigger signal (adtrg) is intput, a/d conversion of the voltage applied to the analog input pin specified by the analog input channel specification register (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is not started until a new external trigger signal is input. if ads0 is rewritten during a/d conversion operation, the converter suspends a/d conversion and waits for a new external trigger signal to be input. when the external trigger input signal is reinput, a/d conversion is carried out from the beginning. if ads0 is rewritten during a/d conversion waiting, a/d conversion starts when the following external trigger input signal is input. if data with adcs0 set to 0 is written to adm0 during a/d conversion, the a/d conversion operation stops immediately. caution when p03/intp3/adtrg is used as the external trigger input (adtrg), specify the valid edge by bits 1, 2 (ega00, ega01) of a/d converter mode register (adm0) and set the interrupt mask flag (pmk3) to 1. figure 14-7. a/d conversion by hardware start (when falling edge is specified) a/d conversion adcr0 adtrg intad0 adm0 set adcs0 = 1, trg0 = 1 ads0 rewrite standby state anin anin standby state anin standby state anim anim anim anin anin anin anim anim remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7
256 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) (2) a/d conversion by software start when bit 6 (trg0) and bit 7 (adcs0) of the a/d converter mode register (adm0) are set to 0 and 1, respectively, a/d conversion of the voltage applied to the analog input pin specified by the analog input channel specification register (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is immediately started. a/d conversion operations are repeated until new data is written to ads0. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion operation and a/d conversion of the new selected analog input channel starts. if data with adcs0 set to 0 is written to adm0 during a/d conversion, the a/d conversion operation stops immediately. figure 14-8. a/d conversion by software start adm0 set adcs0 = 1, trg0 = 0 ads0 rewrite adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion suspended; conversion results are not stored remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7
257 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) 14.5 a/d converter cautions (1) current consumption in standby mode a/d converter stops operating in the standby mode. at this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (adcs0) of the a/d converter mode register (adm0) to 0). figure 14-9 shows how to reduce the current consumption in the standby mode. figure 14-9. example of method of reducing current consumption in standby mode av ref av ss p-ch series resistor string adcs0 (2) input range of ani0 to ani7 the input voltages of ani0 to ani7 should be within the specification range. in particular, if a voltage higher than av ref or lower than av ss is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations <1> contention between a/d conversion result register (adcr0) write and adcr0 read by instruction upon the end of conversion adcr0 read is given priority. after the read operation, the new conversion result is written to adcr0. <2> contention between adcr0 write and external trigger signal input upon the end of conversion the external trigger signal is not accepted during a/d conversion. therefore, the external trigger signal is not accepted during adcr0 write. <3> contention between adcr0 write and a/d converter mode register (adm0) write or analog input channel specification register (ads0) write adm0 or ads0 write is given priority. adcr0 write is not performed, nor is the conversion end interrupt request signal (intad0) generated. <4> noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to pin av ref and pins ani0 to ani7. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 14-10 to reduce noise.
258 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) figure 14-10. analog input pin connector reference voltage input c = 100 to 1000pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref v dd0 av dd av ss v ss0 ani0 to ani7 (5) ani0 to ani7 the analog input pins (ani0 to ani7) also function as input/output port pins (p10 to p17). when a/d conversion is performed with any of pins ani0 to ani7 selected, do not execute an input instruction to port 1 while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) av ref pin input impedance a series resistor string of approx. 10 k w is connected between the av ref pin and the av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in parallel. this may cause a greater reference voltage error. (7) interrupt request flag (adif0) the interrupt request flag (adif0) is not cleared even if the analog input channel specification register (ads0) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads0 rewrite. caution is therefore required since, at this time, when adif0 is read immediately just after the ads0 rewrite, adif0 is set despite the fact that the a/d conversion for the post-change analog input has not ended. when a/d conversion is restarted after it is stopped, clear adif0 before restart.
259 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) figure 14-11. a/d conversion end interrupt request generation timing adm0 rewrite (start of anin conversion) adif is set but anim conversion has not ended. a/d conversion adcr0 intad0 anin anin anim anim anin anin anim anim ads0 rewrite (start of anin conversion) remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7
260 chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) (8) av dd pin the av dd pin is the analog circuit power supply pin. it supplies power to the input circuits of the ani0 to ani7 pins. therefore, be sure to apply the same potential as v dd0 to this pin even for applications designed to switch to a backup battery for power supply. figure 14-12. av dd pin connection main power supply capacitor for back-up av ref v dd0 av ss av dd v ss0 (9) conversion results just after a/d conversion start the first a/d conversion value just after a/d conversion operations start may not fall within the rating. polling a/d conversion end interrupt request (intad0) and take measures such as removing the first conversion results. (10) a/d conversion result register (adcr0) read operation when writing is performed to the a/d converter mode register (adm0) and analog input channel specification register (ads0), the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0, ads0. using a timing other than the above may cause an incorrect conversion result to be read.
261 chapter 15 serial interface outline the m pd780024, 780034 subseries and the m pd780024y, 780034y subseries have differences in their interfaces. these differences are listed in table 15-1. table 15-1. differences between m pd780024, 780034 subseries and m pd780024y, 780034y subseries item m pd780024, 780034 m pd780024y, 780034y relevant section uart0 ? chapter 16 sio3 sio30 ? chapter 17 sio31 iic0 chapter 18
262 [memo]
263 chapter 16 serial interface (uart0) 16.1 serial interface functions the serial interface (uart0) has the following three modes. (1) operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. for details, see 16.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. in addition, a baud rate can also be defined by dividing clocks input to the asck0 pin. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). for details, see 16.4.2 asynchronous serial interface (uart) mode . (3) infrared data transfer mode for details, see 16.4.3 infrared data transfer mode . figure 16-1 shows a block diagram of the serial interface (uart0) macro. figure 16-1. serial interface (uart0) block diagram internal bus receive buffer register (rxb0) rxd0/p23 txd0/p24 receive shift register (rx0) pe0 fe0 ove0 asynchronous serial interface status register ( asis0) intser0 intst0 baud rate generator p25/ask0 f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 asynchronous serial interface mode register ( asim0) intsr0 receive controller (parity check) transmit shift register (txs0) transmit controller (parity addition)
264 chapter 16 serial interface (uart0) 16.2 serial interface configuration the serial interface (uart0) includes the following hardware. table 16-1. serial interface (uart0) configuration item configuration registers transmit shift register (txs0) receive shift register (rx0) receive buffer register (rxb0) control registers asynchronous serial interface mode register (asim0) asynchronous serial interface status register (asis0) baud rate generator control register (brgc0) (1) transmit shift register (txs0) this is the register for setting transmit data. data written to txs0 is transmitted as serial data. when the data length is set as 7 bits, bits 0 to 6 of the data written to txs0 are transferred as transmit data. writing data to txs0 starts the transmit operation. txs0 can be written by an 8-bit memory manipulation instruction. it cannot be read. reset input sets txs0 to ffh. caution do not write to txs0 during a transmit operation. the same address is assigned to txs0 and the receive buffer register (rxb0). a read operation reads values from rxb0. (2) receive shift register (rx0) this register converts serial data input via the rxd0 pin to parallel data. when one byte of data is received at this register, the receive data is transferred to the receive buffer register (rxb0). rx0 cannot be manipulated directly by a program. (3) receive buffer register (rxb0) this register is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred from the receive shift register (rx0). when the data length is set as 7 bits, receive data is sent to bits 0 to 6 of rxb0. in this case, the msb of rxb0 always becomes 0. rxb0 can be read by an 8-bit memory manipulation instruction. it cannot be written to. reset input sets rxb0 to ffh. caution the same address is assigned to rxb0 and the transmit shift register (txs0). during a write operation, values are written to txs0. (4) transmission control circuit the transmission control circuit controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to the transmit shift register (txs0), based on the values set to the asynchronous serial interface mode register (asim0).
265 chapter 16 serial interface (uart0) (5) reception control circuit the reception control circuit controls receive operations based on the values set to the asynchronous serial interface mode register (asim0). during a receive operation, it performs error checking, such as for parity errors, and sets various values to the asynchronous serial interface status register (asis0) according to the type of error that is detected. 16.3 registers to control serial interface the serial interface (uart0) uses the following three types of registers for control functions. ? asynchronous serial interface mode register (asim0) ? asynchronous serial interface status register (asis0) ? baud rate generator control register (brgc0) (1) asynchronous serial interface mode register (asim0) this is an 8-bit register that controls serial interface (uart0)s serial transfer operations. asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets asim0 to 00h. figure 16-2 shows the format of asim0. caution in uart mode, set the port mode register (pmxx) as follows. set the output latch to 0. ? during receive operation set p23 (rxd0) to input mode (pm23 = 1) ? during transmit operation set p24 (txd0) to output mode (pm24 = 0) ? during transmit/receive operation set p23 (rxd0) to input mode, and p24 to output mode
266 chapter 16 serial interface (uart0) figure 16-2. asynchronous serial interface mode register (asim0) format address: ffa0h after reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (t x d0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt request is issued when an error occurs 1 receive completion interrupt request is not issued when an error occurs irdam0 operation specified for infrared data transfer mode note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. the uart/infrared data transfer mode specification is controlled by txe0 and rxe0. 2. when using infrared data transfer mode, be sure to set 10h to the baud rate generator control register (brgc0). caution do not switch the operation mode until the current serial transmit/receive operation has stopped.
267 chapter 16 serial interface (uart0) (2) asynchronous serial interface status register (asis0) when a receive error occurs during uart mode, this register indicates the type of error. asis0 can be read by an 8-bit memory manipulation instruction. reset input sets asis0 to 00h. figure 16-3. asynchronous serial interface status register (asis0) format address: ffa1h after reset: 00h r symbol 7 6 5 43210 asis0 0 0 0 0 0 pe0 fe0 ove0 pe0 parity error flag 0 no parity error 0 parity error (incorrect parity bit detected) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if a stop bit length is set to two bits by setting bit 2 (sl0) in the asynchronous serial interface mode register (asim0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb0) when an overrun error has occurred. until the contents of rxb0 are read, further overrun errors will occur when receiving data. (3) baud rate generator control register (brgc0) this register sets the serial clock for serial interface. brgc0 can be set by an 8-bit memory manipulation instruction. reset input sets brgc0 to 00h. figure 16-4 shows the format of brgc0.
268 chapter 16 serial interface (uart0) figure 16-4. baud rate generator control register (brgc0) format address: ffa2h after reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 (f x = 8.38 mhz) tps02 tps01 tps00 source clock selection for 5-bit counter n 0 0 0 p25/asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 mdl03 mdl02 mdl01 mdl00 input clock selection for baud rate generator k 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibit cautions 1. writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc0 during a communication operation. 2. set 10h to brgc0 when using in infrared data transfer mode. remarks 1. f sck : source clock for 5-bit counter 2. n : value set via tps00 to tps02 (0 n 7) 3. k : value set via mdl00 to mdl03 (0 k 14)
269 chapter 16 serial interface (uart0) 16.4 serial interface operations this section explains the three modes of the serial interface (uart0). 16.4.1 operation stop mode because serial transfer is not performed during this mode, the power consumption can be reduced. in addition, pins can be used as ordinary ports. (1) register settings operation stop mode are set by the asynchronous serial interface mode register (asim0). asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets asim0 to 00h. address: ffa0h after reset: 00h r/w symbol 7 6 5 43210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (txd0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) caution do not switch the operation mode until the current serial transmit/receive operation has stopped. 16.4.2 asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted or received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). (1) register settings uart mode settings are performed by the asynchronous serial interface mode register (asim0), asynchronous serial interface status register (asis0), and the baud rate generator control register (brgc0). (a) asynchronous serial interface mode register (asim0) asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets asim0 to 00h. caution in uart mode, set the port mode register (pmxx) as follows. set the output latch to 0. ? during receive operation set p23 (rxd0) to input mode (pm23 = 1) ? during transmit operation set p24 (txd0) to output mode (pm24 = 0) ? during transmit/receive operation set p23 (rxd0) to input mode, and p24 to output mode
270 chapter 16 serial interface (uart0) address: ffa0h after reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (txd0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 0 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt request is issued when an error occurs 1 receive completion interrupt request is not issued when an error occurs irdam0 operation specified for infrared data transfer mode note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. the uart/infrared data transfer mode specification is controlled by txe0 and rxe0. 2. when using infrared data transfer mode, be sure to set the baud rate generator control register (brgc0) to 10h. caution do not switch the operation mode until the current serial transmit/receive operation has stopped.
271 chapter 16 serial interface (uart0) (b) asynchronous serial interface status register (asis0) asis0 can be read by an 8-bit memory manipulation instruction. reset input sets asis0 to 00h. address: ffa1h after reset: 00h r symbol 7 6 5 43210 asis0 0 0 0 0 0 pe0 fe0 ove0 pe0 parity error flag 0 no parity error 1 parity error (incorrect parity bit detected) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if a stop bit length is set to two bits by setting bit 2 (sl0) in the asynchronous serial interface mode register (asim0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb0) when an overrun error has occurred. until the contents of rxb0 are read, further overrun errors will occur when receiving data.
272 chapter 16 serial interface (uart0) (c) baud rate generator control register (brgc0) brgc0 can be set by an 8-bit memory manipulation instruction. reset input sets brgc0 to 00h. address: ffa2h after reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 (f x = 8.38 mhz) tps02 tps01 tps00 source clock selection for 5-bit counter n 0 0 0 p25/asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 mdl03 mdl02 mdl01 mdl00 input clock selection for baud rate generator k 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibit cautions 1. writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc0 during a communication operation. 2. set 10h to brgc0 when using infrared data transfer mode. remarks 1. f sck : source clock for 5-bit counter 2. n : value set via tps00 to tps02 (0 n 7) 3. k : value set via mdl00 to mdl03 (0 k 14)
273 chapter 16 serial interface (uart0) the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. ? transmit/receive clock generation for baud rate by using main system clock the main system clock is divided to generate the transmit/receive clock. the baud rate generated from the main system clock is determined according to the following formula. [baud rate] = f x [hz] 2 n+1 (k + 16) f x : oscillation frequency of main system clock n : value set via tps00 to tps02 (0 n 7) for details, see table 16-2. k : value set via mdl00 to mdl03 (0 k 14) table 16-2 shows the relationship between the 5-bit counters source clock assigned to bits 4 to 6 (tps00 to tps02) of brgc0 and the n value in the above formula. table 16-2. relationship between 5-bit counters source clock and n value tps02 tps01 tps00 5-bit counters source clock selected n 0 0 0 p25/asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 remark f x : oscillation frequency of main system clock
274 chapter 16 serial interface (uart0) ? error tolerance range for baud rates the tolerance range for baud rates depends on the number of bits per frame and the counters division rate [1/(16 + k)]. table 16-3 describes the relationship between the main system clock and the baud rate and figure 16- 5 shows an example of a baud rate error tolerance range. table 16-3. relationship between main system clock and baud rate baud rate f x = 8.386 mhz f x = 8.000 mhz f x = 7.3728 mhz f x = 5.000 mhz f x = 4.1943 mhz (bps) brgc0 err (%) brgc0 err (%) brgc0 err (%) brgc0 err (%) brgc0 err (%) 600 C C C C C C C C 7bh 1.14 1200 7bh 1.10 7ah 0.16 78h 0 70h 1.73 6bh 1.14 2400 6bh 1.10 6ah 0.16 68h 0 60h 1.73 5bh 1.14 4800 5bh 1.10 5ah 0.16 58h 0 50h 1.73 4bh 1.14 9600 4bh 1.10 4ah 0.16 48h 0 40h 1.73 3bh 1.14 19200 3bh 1.10 3ah 0.16 38h 0 30h 1.73 2bh 1.14 31250 31h C1.3 30h 0 2dh 1.70 24h 0 21h C1.3 38400 2bh 1.10 2ah 0.16 28h 0 20h 1.73 1bh 1.14 76800 1bh 1.10 1ah 0.16 18h 0 10h 1.73 C C 115200 12h 1.10 11h 2.12 10h 0CCCC infrared 65536 bps 62500 bps 115200 bps 39063 bps 32768 bps data transfer mode note note the uart/infrared data transfer mode specification is controlled by txe0 and rxe0. when using the infrared data transfer mode, be sure to set the baud rate generator control register (brgc0) as follows. ? k = 0 (mdl0 to mdl3 = 0000) ? n = 1 (tps00 to tps02 = 001) remark f x : oscillation frequency of main system clock n : value set via tps00 to tps02 (0 n 7) k : value set via mdl00 to mdl03 (0 k 14)
275 chapter 16 serial interface (uart0) figure 16-5. error tolerance (when k = 0), including sampling errors basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t) enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t) enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t remark t: 5-bit counters source clock cycle baud rate error tolerance (when k = 0) = 15.5 100 = 4.8438 (%) 320
276 chapter 16 serial interface (uart0) (2) communication operations (a) data format figure 16-6 shows the format of the transmit/receive data. figure 16-6. format of transmit/receive data in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame character bits 1 data frame consists of the following bits. ? start bit ............. 1 bit ? character bits ... 7 bits or 8 bits ? parity bit ........... even parity, odd parity, zero parity, or no parity ? stop bit(s) ......... 1 bit or 2 bits the asynchronous serial interface mode register (asim0) is used to set the character bit length, parity selection, and stop bit length within each data frame. when 7 bits is selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to 0. the asim0 and the baud rate generator control register (brgc0) are used to set the serial transfer rate. if a receive error occurs, information about the receive error can be recognized by reading the asynchronous serial interface status register (asis0).
277 chapter 16 serial interface (uart0) (b) parity types and operations the parity bit is used to detect bit errors in transfer data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. when zero parity or no parity is set, errors are not detected. (i) even parity ? during transmission the number of bits in transmit data that includes a parity bit is controlled so that there are an even number of bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of bits whose value is 1: the parity bit is 1 if the transmit data contains an even number of bits whose value is 1: the parity bit is 0 ? during reception the number of bits whose value is 1 is counted among the transfer data that include a parity bit, and a parity error occurs when the counted result is an odd number. (ii) odd parity ? during transmission the number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of bits whose value is 1: the parity bit is 0 if the transmit data contains an even number of bits whose value is 1: the parity bit is 1 ? during reception the number of bits whose value is 1 is counted among the transfer data that include a parity bit, and a parity error occurs when the counted result is an even number. (iii) zero parity during transmission, the parity bit is set to 0 regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will occur regardless of whether the parity bit is a 0 or a 1. (iv) no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will occur.
278 chapter 16 serial interface (uart0) (c) transmission the transmit operation is started when transmit data is written to the transmit shift register (txs0). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting the transmit operation shifts out the data in txs0, thereby emptying txs0, after which a transmit completion interrupt request (intst0) is issued. the timing of the transmit completion interrupt request is shown in figure 16-7. figure 16-7. timing of asynchronous serial interface transmit completion interrupt request (i) stop bit length: 1 bit txd0 (output) d0 d1 d2 d6 d7 parity stop start intst0 txd0 (output) d0 d1 d2 d6 d7 parity start intst0 stop caution do not rewrite to the asynchronous serial interface mode register (asim0) during a transmit operation. rewriting asim0 register during a transmit operation may disable further transmit operations (in such cases, enter a reset to restore normal operation). whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt request (intst0) or the interrupt request flag (stif0) that is set by intst0. (ii) stop bit length: 2 bits
279 chapter 16 serial interface (uart0) (d) reception the receive operation is enabled when 1 is set to bit 6 (rxe0) of the asynchronous serial interface mode register (asim0), and input via the rxd0 pin is sampled. the serial clock specified by asim0 is used to sample the rxd0 pin. when the rxd0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. if sampling the rxd0 pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once reception of one data frame is completed, the receive data in the shift register is transferred to the receive buffer register (rxb0) and a receive completion interrupt request (intsr0) occurs. even if an error has occurred, the receive data in which the error occurred is still transferred to rxb0. when asim0 bit 1 (isrm0) is cleared (0) upon occurrence of an error, intsr0 occurs (see figure 16-9). when isrm0 bit is set (1), intsr0 does not occurr. if the rxe0 bit is reset (to 0) during a receive operation, the receive operation is stopped immediately. at this time, the contents of rxb0 and asis0 do not change, nor does intsr0 or intser0 occur. figure 16-8 shows the timing of the asynchronous serial interface receive completion interrupt request. figure 16-8. timing of asynchronous serial interface receive completion interrupt request rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr0 caution be sure to read the contents of the receive buffer register (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read.
280 chapter 16 serial interface (uart0) (e) receive errors three types of errors can occur during a receive operation: parity error, framing error, or overrun error. if, as the result of data reception, an error flag is set to the asynchronous serial interface status register (asis0), a receive error interrupt request (intser0) will occur. receive error interrupts requests are generated before receiving completion interrupts request (intsr0). table 16-4 lists the causes behind receive errors. as part of receive error interrupt request (intser0) servicing, the contents of asis0 can be read to determine which type of error occurred during the receive operation (see table 16-4 and figure 16-9). the contents of asis0 are reset (to 0) when the receive buffer register (rxb0) is read or when the next data is received (if the next data contains an error, its error flag will be set). table 16-4. causes of receive errors receive error cause asis0 value parity error parity specified during transmission does not match parity of receive data 04h framing error stop bit was not detected 02h overrun error reception of the next data was completed before data was read from the 01h receive buffer register figure 16-9. receive error timing rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr0 note intser0 (when framing/overrun error occurs) intser0 (when parity error occurs) note if a receive error occurs when isrm0 bit has been set (1), intsr0 does not occur. cautions 1. the contents of asis0 are reset (to 0) when the receive buffer register (rxb0) is read or when the next data is received. to obtain information about the error, be sure to read the contents of asis0 before reading rxb0. 2. be sure to read the contents of the receive buffer register (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read.
281 chapter 16 serial interface (uart0) 16.4.3 infrared data transfer mode in infrared data transfer mode, the following data format pulse output and pulse receiving are enabled. the relationship between the main system clock and baud rate is shown in table 16-3. (1) data format figure 16-10 compares the data format used in uart mode with that used in infrared data transfer mode. the ir (infrared) frame corresponds to the bit string of the uart frame, which consists of pulses C a start bit, eight data bits, and a stop bit. the length of the electrical pulses that are used to transmit and receive in an ir frame is 3/16 the length of the cycle time for one bit (i.e., the bit time). this pulse (whose width is 3/16 the length of one bit time) rises from the middle of the bit time (see the figure below). 0 start bit 1 d0 0 d1 1 d2 0 d3 0 d4 1 d5 1 d6 0 d7 1 stop bit uart frame data bits start bit 10100110 stop bit ir frame data bits pulse width = 3/16 bit time bit time 0 1 bit time pulse width = 3/16 bit time figure 16-10. data format comparison between infrared data transfer mode and uart mode
282 chapter 16 serial interface (uart0) (2) bit rate and pulse width table 16-5 lists bit rates, bit rate error tolerances, and pulse width values. table 16-5. bit rate and pulse width values bit rate bit rate error tolerance pulse width minimum value 3/16 pulse width maximum pulse width (kbits/s) (% of bit rate) ( m s) note 2 ( m s) ( m s) 115.2 note 1 +/C 0.87 1.41 1.63 2.71 notes 1. at the operation time with f x = 7.3728 mhz 2. when a digital noise elimination circuit is used in a microcontroller operating at 1.41 mhz or above. caution when using the baud rate generator control register (brgc0) in infrared data transfer mode, set 10h to it. remark f x : main system clock oscillation frequency
283 chapter 16 serial interface (uart0) (3) input data and internal signals ? transmit operation timing uart output data uart (inverted data) infrared data transfer enable signal txd0 pin output signal start bit stop bit ? receive operation timing data reception is delayed for one-half of the specified baud rate. uart transfer data rxd0 input edge detection sampling clock start bit stop bit receive rate conversion data sampling timing
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285 chapter 17 serial interface (sio3) the serial interface (sio3) incorporates two 3-wire serial i/o mode channels (sio30, sio31). these two channels have exactly the same functions. therefore, unless otherwise specified, the sio30 is used throughout this chapter to describe the functions of both the sio30 and sio31. if using the sio31, refer to table 17-1 for the register, bit, and pin names. caution the m pd780024y and 780034y subseries products do not have the sio31. table 17-1. sio30 and sio31 naming differences item sio30 sio31 pins p20/si30 p34/si31 p21/so30 p35/so31 p22/sck30 p36/sck31 serial operation mode register 3 csim30 csim31 address of serial operation mode register 3 ffb0h ffb8h bit name of serial operation mode register 3 csie30 csie31 mode30 mode31 scl301 scl311 scl300 scl310 serial i/o shift register 3 sio30 sio31 address of serial i/o shift register 3 ff1ah ff1bh interrupt request intcsi30 intcsi31 interrupt control register and bits mentioned in this chapter csiif30 csiif31 csimk30 csimk31 csipr30 csipr31
286 chapter 17 serial interface (sio3) 17.1 serial interface functions the serial interface (sio3) has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. for details, see 17.4.1 operation stop mode . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck30), serial output line (so30), and serial input line (si30). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit of the serial transferred 8-bit data is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o incorporating a clock-synchronous serial interface, or a display controller, etc. for details see 17.4.2 3-wire serial i/o mode . figure 17-1 shows a block diagram of the serial interface (sio30). figure 17-1. serial interface (sio30) block diagram internal bus 8 8 direction control circuit serial clock control circuit serial clock counter interruption request signal generator selector serial i/o shift register 30 (sio30) si30/p20 so30/p21 sck30/p22 intcsi30 f x /2 3 f x /2 4 f x /2 5
287 chapter 17 serial interface (sio3) 17.2 serial interface configuration the serial interface (sio30) includes the following hardware. table 17-2. serial interface (sio30) configuration item configuration registers serial i/o shift register 30 (sio30) control registers serial operation mode register 30 (csim30) (1) serial i/o shift register 30 (sio30) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sio30 is set by an 8-bit memory manipulation instruction. when 1 is set to bit 7 (csie30) of the serial operation mode register 30 (csim30), a serial operation can be started by writing data to or reading data from sio30. when transmitting, data written to sio30 is output to the serial output (so30). when receiving, data is read from the serial input (si30) and written to sio30. reset input resets sio30 to 00h. caution do not access sio30 during a transmit operation unless the access is triggered by a transfer start. (read operation is disabled when mode0 = 0 and write operation is disabled when mode0 = 1.)
288 chapter 17 serial interface (sio3) 17.3 register to control serial interface the serial interface (sio30) uses the following type of register to control functions. ? serial operation mode register 30 (csim30) (1) serial operation mode register 30 (csim30) this register is used to enable or disable sio30s serial clock, operation modes, and specific operations. csim30 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim30 to 00h. caution in 3-wire serial i/o mode, set the port mode register (pmxx) as follows. set the output latch to 0. ? during serial clock output (master transmission or master reception) set p22 (sck30) to output mode (pm22 = 0) ? during serial clock input (slave transmission or slave reception) set p22 to input mode (pm22 = 1) ? during transmit/transmit and receive mode set p21 (so30) to output mode (pm21 = 0) ? during receive mode set p20 (si30) to input mode (pm20 = 1) figure 17-2. serial operation mode register 30 (csim30) format address: ffb0h after reset: 00h r/w symbol 76543210 csim30 csie30 0 0 0 0 mode0 scl301 scl300 csie30 enable/disable specification for sio30 shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial function + port function note 2 mode0 transfer operation modes and flags operation mode transfer start trigger so30 output 0 transmit/transmit and receive mode write to sio30 normal output 1 receive-only mode read from sio30 fixed at low level scl301 scl300 clock selection 0 0 external clock input to sck30 01f x /2 3 (1.05 mhz) 10f x /2 4 (524 khz) 11f x /2 5 (262 khz)
289 chapter 17 serial interface (sio3) notes 1. when csie30 = 0 (sio30 operation stop status), the pins si30, so30, and sck30 can be used for port functions. 2. when csie30 = 1 (sio30 operation enabled state), the si30 pin can be used as a port pin if only the send function is used, and the so30 pin can be used as a port pin if only the receive-only mode is used. remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz. 17.4 serial interface operations this section explains on two modes of serial interface sio3. 17.4.1 operation stop mode because the serial transfer is not performed during this mode, the power consumption can be reduced. in addition, pins can be used as normal i/o ports. (1) register settings operation stop mode are set by the serial operation mode register 30 (csim30). csim30 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. address: ffb0h after reset: 00h r/w symbol 7 6 5 43210 csim30 csie30 0 0 0 0 mode0 scl301 scl300 csie30 sio30 operation enable/disable specification shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial function + port function note 2 notes 1. when csie30 = 0 (sio30 operation stop status), the pins si30, so30, and sck30 can be used for port functions. 2. when csie30 = 1 (sio30 operation enabled state), the si30 pin can be used as a port pin if only the send function is used, and the so30 pin can be used as a port pin if only the receive-only mode is used.
290 chapter 17 serial interface (sio3) 17.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection to a peripheral i/o incorporating a clock-synchronous serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sck30), serial output line (so30), and serial input line (si30). (1) register settings 3-wire serial i/o mode is set by the serial operation mode register 30 (csim30). csim30 can be set by a 1-bit or 8-bit memory manipulation instructions. reset input sets csim30 to 00h . caution in 3-wire serial i/o mode, set the port mode register (pmxx) as follows. set the output latch to 0. ? during serial clock output (master transmission or master reception) set p22 (sck30) to output mode (pm22 = 0) ? during serial clock input (slave transmission or slave reception) set p22 to input mode (pm22 = 1) ? during transmit/transmit and receive mode set p21 (so30) to output mode (pm21 = 0) ? during receive mode set p20 (si30) to input mode (pm20 = 1) address: ffb0h after reset: 00h r/w symbol 76543210 csim30 csie30 0 0 0 0 mode0 scl301 scl300 csie30 enable/disable specification for sio30 shift register operation serial counter port 0 operation stop clear port function note 1 1 operation enable count operation enable serial function + port function note 2 mode0 transfer operation modes and flags operation mode transfer start trigger so30 output 0 transmit/transmit and receive mode write to sio30 normal output 1 receive-only mode read from sio30 fixed at low level scl301 scl300 clock selection 0 0 external clock input to sck30 01f x /2 3 (1.05 mhz) 10f x /2 4 (524 khz) 11f x /2 5 (262 khz) notes 1. when csie30 = 0 (sio30 operation stop status), the pins si30, so30, and sck30 can be used for port functions. 2. when csie30 = 1 (sio30 operation enabled state), the si30 pin can be used as a port pin if only the send function is used, and the so30 pin can be used as a port pin if only the receive-only mode is used.
291 chapter 17 serial interface (sio3) remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses are for operation with f x = 8.38 mhz. (2) communication operations in the three-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is sent or received in synchronization with the serial clock. the serial i/o shift register 30 (sio30) is shifted in synchronization with the falling edge of the serial clock. transmission data is held in the so30 latch and is output from the so30 pin. data that is received via the si30 pin in synchronization with the rising edge of the serial clock is latched to sio30. completion of an 8-bit transfer automatically stops operation of sio30 and sets interrupt request flag (csiif30). figure 17-3. timing of 3-wire serial i/o mode (3) transfer start a serial transfer starts when the following two conditions have been satisfied and transfer data has been set (or read) to serial i/o shift register 30 (sio30). ? the sio30 operation control bit (csie30) = 1 ? after an 8-bit serial transfer, either the internal serial clock is stopped or sck30 is set to high level. ? transmit/transmit and receive mode when csie30 = 1 and mode0 = 0, transfer starts when writing to sio30. ? receive-only mode when csie30 = 1 and mode0 = 1, transfer starts when reading from sio30. caution after data has been written to sio30, transfer will not start even if the csie30 bit value is set to 1. completion of an 8-bit transfer automatically stops the serial transfer operation and interrupt request flag (csiif30) is set. si30 di7 di6 di5 di4 di3 di2 di1 di0 csiif30 sck30 1 so30 do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronization with the sck30 falling edge
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293 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.1 serial interface functions the serial interface (iic0) has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. this mode complies with the i 2 c bus format and can output start condition, data, and stop condition data segments when transmitting via the serial data bus. these data segments are automatically detected by hardware during reception. since scl0 and sda0 are open-drain outputs, the iic0 requires pull-up resistors for the serial clock line (scl0) and the serial data bus line (sda0).
294 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-1 shows a block diagram of serial interface (iic0). figure 18-1. serial interface (iic0) block diagram internal bus iic status register (iics0) iic control register (iicc0) slave address register (sva0) noise elimination circuit noise elimination circuit coincidence signal iic shift register (iic0) so0 latch iice0 d set clear q cl01, cl00 sda0/p32 scl0/p33 n-ch open- drain output data hold time correction circuit ack detection circuit wake up control circuit ack detection circuit stop condition detection circuit serial clock counter interrupt request signal generator serial clock control circuit serial clock wait control circuit prescaler intiic0 f x cld0 iic clock select register (iiccl0) internal bus lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detection circuit dad0 smc0 dfc0 cl00
295 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-2 shows a serial bus configuration example. figure 18-2. serial bus configuration example using i 2 c bus sda0 scl0 sda0 +v dd0 +v dd0 scl0 sda0 scl0 slave cpu3 address 2 sda0 scl0 slave ic address 3 sda0 scl0 slave ic address n master cpu1 slave cpu1 serial data bus serial clock master cpu2 slave cpu2 address 1
296 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.2 serial interface configuration the serial interface (iic0) includes the following hardware. table 18-1. serial interface (iic0) configuration item configuration registers iic shift register (iic0) slave address register (sva0) control registers iic control register (iicc0) iic status register (iics0) iic clock select register (iiccl0) (1) iic shift register (iic0) iic0 is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data. iic0 can be used for both transmission and reception. write and read operations to iic0 are used to control the actual transmit and receive operations. iic0 is set by an 8-bit memory manipulation instruction. reset input sets the iic0 00h. (2) slave address register (sva0) this register sets local addresses when in slave mode. sva0 is set by an 8-bit memory manipulation instruction. reset input sets sva0 to 00h. (3) so0 latch the so0 latch is used to retain the sda0 pins output level. (4) wake-up control circuit this circuit generates an interrupt request when the address received by this register matches the address value set to the slave address register (sva0) or when an extension code is received. (5) clock selector this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt request is generated following either of two triggers. ? eighth or ninth clock of the serial clock (set by wtim0 bit) note ? interrupt request generated when a stop condition is detected (set by spie0 bit) note note wtim0 bit : bit 3 of the iic control register (iicc0) spie0 bit : bit 4 of the iic control register (iicc0)
297 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (8) serial clock control circuit during master mode, this circuit generates the clock output via the scl0 pin from a sampling clock. (9) serial clock wait control circuit this circuit controls the wait timing. (10) ack output circuit, stop condition detection circuit, start condition detection circuit, and ack detection circuit these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the serial clock. 18.3 registers to control serial interface serial interface (iic0) is controlled via three types of registers. ? iic control register (iicc0) ? iic status register (iics0) ? iic clock select register (iiccl0) the following registers are also used. ? iic shift register (iic0) ? slave address register (sva0) (1) iic control register (iicc0) this register is used to enable/disable i 2 c operations, set wait timing, and set other i 2 c operations. iicc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets iicc0 to 00h. caution in i 2 c bus mode, set the port mode register (pmxx) as follows. set the output latch to 0. ? set p32 (sda0) to output mode (pm32 = 0) ? set p33 (scl0) to output mode (pm33 = 0)
298 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-3. iic control register (iicc0) format (1/3) address: ffa8h after reset: 00h r/w symbol 76543210 iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c operation enable 0 stops operation. presets expansion register (iics0). stops internal operation. 1 enables operation. condition for clearing (iice0 = 0) condition for setting (iice0 = 1) ? cleared by instruction ? set by instruction ? when reset is input lrel0 exit from communications 0 normal operation 1 this exits from the current communications operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines go into the high impedance state. the following flags are cleared. ? std0 ? ackd0 ? trc0 ? coi0 ? exc0 ? msts0 ? stt0 ? spt0 the standby mode following exit from communications remains in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code reception occurs after the start condition. condition for clearing (lrel0 = 0) note condition for setting (lrel0 = 1) ? automatically cleared after execution ? set by instruction ? when reset is input wrel0 cancel wait 0 does not cancel wait 1 cancels wait. this setting is automatically cleared after wait is canceled. condition for clearing (wrel0 = 0) note condition for setting (wrel0 = 1) ? automatically cleared after execution ? set by instruction ? when reset is input spie0 enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 = 0) note condition for setting (spie0 = 1) ? cleared by instruction ? set by instruction ? when reset is input note this flags signal is invalid when iice0 = 0.
299 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-3. iic control register (iicc0) format (2/3) wtim0 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clocks falling edge. master mode : after output of eight clocks, clock output is set to low level and wait is set. slave mode : after input of eight clocks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clocks falling edge. master mode : after output of nine clocks, clock output is set to low level and wait is set. slave mode : after input of nine clocks, the clock is set to low level and wait is set for master device . this bits setting is invalid during an address transfer and is valid after the transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 = 0) note condition for setting (wtim0 = 1) ? cleared by instruction ? set by instruction ? when reset is input acke0 acknowledge control 0 disable acknowledge. 1 enable acknowledge. during the ninth clock period, the sda0 line is set to low level. however, the ack is invalid during address transfers and is valid when exc0 = 1. condition for clearing (acke0 = 0) note condition for setting (acke0 = 1) ? cleared by instruction ? set by instruction ? when reset is input stt0 start condition trigger 0 does not generate a start condition. 1 when bus is released (during stop mode): generates a start condition (for starting as master). the sda0 line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scl0 is changed to low level. when bus is not used: this trigger functions as a start condition reserve flag. when set, it releases the bus and then automatically generates a start condition. wait status (during master mode): generates a restart condition after wait is released. cautions concerning set timing ? for master reception : cannot be set during transfer. can be set only at the waiting period when acke0 has been set to 0 and slave has been notified of final reception. ? for master transmission : a start condition may not be generated normally during the ack period. therefore, set it during the waiting period. ? cannot be set at the same time as spt0 condition for clearing (stt0 = 0) note condition for setting (stt0 = 1) ? cleared by instruction ? set by instruction ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when lrel0 = 1 ? when reset is input note this flags signal is invalid when iice0 = 0.
300 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-3. iic control register (iicc0) format (3/3) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master devices transfer). after the sda0 line goes to low level, either set the scl0 line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sda0 line changes from low level to high level and a stop condition is generated. cautions concerning set timing ? for master reception : cannot be set during transfer. can be set only at the waiting period when acke0 has been set to 0 and slave has been notified of final reception. ? for master transmission: a stop condition cannot be generated normally during the ack0 period. therefore, set it during the waiting period. ? cannot be set at the same time as stt0. ? spt0 can be set only when in master mode. note 1 ? when wtim0 has been set to 0, if spt0 is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high level period of the ninth clock. when a ninth clock must be output, wtim0 should be changed from 0 to 1 during the wait period following output of eight clocks, and spt0 should be set during the wait period that follows output of the ninth clock. condition for clearing (spt0 = 0) note 2 condition for setting (spt0 = 1) ? cleared by instruction ? set by instruction ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when lrel0 = 1 ? when reset is input notes 1. set spt0 only during master mode. however, you must set spt0 and generate a stop condition before the first stop condition is detected following the switch to operation enable status. for details, see 18.5.15 other cautions . 2. this flags signal is invalid when iice0 = 0. caution when bit 3 (trc0) of the iic status register (iics0) is set to 1, wrel0 is set during the ninth clock and wait is canceled, after which trc0 is cleared and the sda0 line is set for high impedance. remarks 1. std0 : bit 1 of iic status register (iics0) ackd0 : bit 2 of iic status register (iics0) trc0 : bit 3 of iic status register (iics0) coi0 : bit 4 of iic status register (iics0) exc0 : bit 5 of iic status register (iics0) msts0 : bit 7 of iic status register (iics0) 2. bits 0 and 1 (spt0, stt0) become 0 when they are read after data setting.
301 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (2) iic status register (iics0) this register indicates the status of the i 2 c. iics0 can be set by a 1-bit or 8-bit memory manipulation instruction. iics0n is a read-only register. reset input sets the value to 00h. figure 18-4. iic status register format (iics0) (1/3) address: ffa9h after reset: 00h r symbol 76543210 iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 = 0) condition for setting (msts0 = 1) ? when a stop condition is detected ? when a start condition is generated ? when ald0 = 1 ? cleared by lrel0 = 1 ? when iice0 changes from 1 to 0 ? when reset is input ald0 detection of arbitration loss 0 this status means either that there was no arbitration or that the arbitration result was a win. 1 this status indicates the arbitration result was a loss. msts0 is cleared. condition for clearing (ald0 = 0) condition for setting (ald0 = 1) ? automatically cleared after iics0 is read note ? when the arbitration result is a loss. ? when iice0 changes from 1 to 0 ? when reset is input exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 = 0) condition for setting (exc0 = 1) ? when a start condition is detected ? when the high-order four bits of the received ? when a stop condition is detected address data is either 0000 or 1111 ? cleared by lrel0 = 1 (set at the rising edge of the eighth clock). ? when iice0 changes from 1 to 0 ? when reset is input note this register is also cleared when a bit manipulation instruction is executed for bits other than iics0.
302 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-4. iic status register (iics0) format (2/3) coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 = 0) condition for setting (coi0 = 1) ? when a start condition is detected ? when the received address matches the local ? when a stop condition is detected address (sva0) ? cleared by lrel0 = 1 (set at the rising edge of the eighth clock). ? when iice0 changes from 1 to 0 ? when reset is input trc0 detection of transmit/receive status 0 receive status (other than transmit status). the sda0 line is set for high impedance. 1 transmit status. the value in the so0 latch is enabled for output to the sda0 line (valid starting at the rising edge of the first bytes ninth clock). condition for clearing (trc0 = 0) condition for setting (trc0 = 1) ? when a stop condition is detected master ? cleared by lrel0 = 1 ? when a start condition is generated ? when iice0 changes from 1 to 0 slave ? cleared by wrel0 = 1 ? when 1 is input by the first bytes lsb ? when ald0 changes from 0 to 1 (transfer direction specification bit) ? when reset is input master ? when 1 is output to the first bytes lsb (transfer direction specification bit) slave ? when a start condition is detected ? when not used for communication ackd0 detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackd0 = 0) condition for setting (ackd0 = 1) ? when a stop condition is detected ? after the sda0 line is set to low level at the ? at the rising edge of the next bytes first clock rising edge of the scl0s ninth clock ? cleared by lrel0 = 1 ? when iice0 changes from 1 to 0 ? when reset is input
303 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-4. iic status register (iics0) format (3/3) std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (std0 = 0) condition for setting (std0 = 1) ? when a stop condition is detected ? when a start condition is detected ? at the rising edge of the next bytes first clock following address transfer ? cleared by lrel0 = 1 ? when iice0 changes from 1 to 0 ? when reset is input spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master devices communication is terminated and the bus is released. condition for clearing (spd0 = 0) condition for setting (spd0 = 1) ? at the rising edge of the address transfer bytes ? when a stop condition is detected first clock following setting of this bit and detection of a start condition ? when iice0 changes from 1 to 0 ? when reset is input remark lrel0 : bit 6 of iic control register (iicc0) iice0 : bit 7 of iic control register (iicc0)
304 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (3) iic clock select register (iiccl0) this register is used to set the transfer clock for the i 2 c bus. iiccl0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets iiccl0 to 00h. figure 18-5. iic clock select register (iiccl0) format (1/2) address: ffaah after reset: 00h r/w note symbol 76543210 iiccl0 0 0 cld0 dad0 smc0 dfc0 0 cl00 cld0 detection of scl0 line level (valid only when iice0 = 1) 0 scl0 line was detected at low level. 1 scl0 line was detected at high level. condition for clearing (cld0 = 0) condition for setting (cld0 = 1) ? when the scl0 line is at low level ? when the scl0 line is at high level ? when iice0 = 0 ? when reset is input dad0 detection of sda0 line level (valid only when iice0 = 1) 0 sda0 line was detected at low level. 1 sda0 line was detected at high level. condition for clearing (dad0 = 0) condition for setting (dad0 = 1) ? when the sda0 line is at low level ? when the sda0 line is at high level ? when iice0 = 0 ? when reset is input smc0 operation mode switching 0 operation in standard mode 1 operation in high-speed mode condition for clearing (smc0 = 0) condition for setting (smc0 = 1) ? cleared by instruction ? set by instruction ? when reset is input note bits 4 and 5 are read-only bits.
305 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-5. iic clock select register (iiccl0) format (2/2) dfc0 control of digital filter operation note 0 digital filter on 1 digital filter off cl00 selection of transfer rate standard mode high-speed mode 0f x /44 (191 khz) f x /24 (350 khz) 1f x /86 (97.5 khz) note the digital filter can be used when in high-speed mode. response time is slower when the digital filter is used. caution stop serial transfer once before rewriting cl00 to other than the same value. remarks 1. iice0: bit 7 of iic control register (iicc0) 2. f x : main system clock oscillation frequency 3. figures in parentheses are for operation with f x = 8.38 mhz. (4) i 2 c shift register (iic0) this register is used for serial transmission/reception (shift operations) that are synchronized with the serial clock. it can be read from or written to in 8-bit units, but data should not be written to iic0 during a data transfer. address: ff1fh after reset: 00h r/w symbol 7 6 5 43210 iic0 (5) slave address register (sva0) this register holds the i 2 cs slave addresses. it can be read from or written to in 8-bit units, but bit 0 is fixed to 0. address: ffabh after reset: 00h r/w symbol 7 6 5 43210 sva0 0
306 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.4 i 2 c bus mode functions 18.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. (1) scl0 this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. (2) sda0 this pin is used for serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open drain outputs, an external pull- up resistor is required. figure 18-6. pin configuration diagram v dd0 v ss0 v ss0 v ss0 v ss0 scl0 sda0 scl0 sda0 v dd0 clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
307 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5 i 2 c bus definitions and control methods the following section describes the i 2 c buss serial data communication format and the signals used by the i 2 c bus. figure 18-7 shows the transfer timing for the start condition, data, and stop condition output via the i 2 c buss serial data bus. figure 18-7. i 2 c buss serial data transfer timing 1-7 8 9 1-7 8 9 1-7 8 9 scl0 sda0 start condition address r/w ack data data stop condition ack ack the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master device. however, in the slave device, the scl0s low level period can be extended and a wait can be inserted. 18.5.1 start conditions a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are signals that the master device outputs to the slave device when starting a serial transfer. the slave device includes hardware for detecting start conditions. figure 18-8. start conditions h scl0 sda0 a start condition is output when the iic control register (iicc0)s bit 1 (stt0) is set (to 1) after a stop condition has been detected (spd0: bit 0 = 1 in the iic status register (iics0)). when a start condition is detected, iics0s bit 1 (std0) is set (to 1).
308 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.2 addresses the address is defined by the 7 bits of data that follow the start condition. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the slave address register (sva0). if the address data matches the sva0 values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition. figure 18-9. address address scl0 1 sda0 intiic0 note 23456789 a6 a5 a4 a3 a2 a1 a0 r/w note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. the slave address and the eighth bit, which specifies the transfer direction as described in 18.5.3 transfer direction specification below, are together written to the iic shift register (iic0) and are then output. received addresses are written to iic0. the slave address is assigned to the high-order 7 bits of iic0. 18.5.3 transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 18-10. transfer direction specification scl0 1 sda0 intiic0 23456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note note intiic0 is not issued if data other than a local address or extension code is received during slave device operation.
309 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.4 acknowledge (ack) signal the acknowledge (ack) signal is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. (a) reception was not performed normally. (b) the final data was received. when the receiving device sets the sda0 line to low level during the ninth clock, the ack signal becomes active (normal receive response). when bit 2 (acke0) of the iic control register (iicc0) is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following the 7 address data bits causes bit 3 (trc0) of the iic status register (iics0) to be set. when this trc0 bits value is 0, it indicates receive mode. therefore, acke0 should be set to 1. when the slave device is receiving (when trc0 = 0), if the slave devices does not need to receive any more data after receiving several bytes, setting acke0 to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trc0 = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting acke0 to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sda line (i.e., stops transmission) during transmission from the slave device. figure 18-11. ack signal scl0 1 sda0 23456789 a6 a5 a4 a3 a2 a1 a0 r/w ack when the local address is received, an ack signal is automatically output in sync with the falling edge of the scls eighth clock regardless of the acke0 value. no ack signal is output if the received address is not a local address. the ack signal output method during data reception is based on the wait timing setting, as described below. ? when 8-clock wait is selected : ack signal is output when acke0 is set to 1 before wait cancellation. ? when 9-clock wait is selected : ack signal is automatically output at the falling edge of the scl0s eighth clock if acke0 has already been set to 1.
310 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. the slave device includes hardware that detects stop conditions. figure 18-12. stop condition h scl0 sda0 a stop condition is generated when bit 0 (spt0) of the iic control register (iicc0) is set (to 1). when the stop condition is detected, bit 0 (spd0) of the iic status register (iics0) is set (to 1) and intiic0 is generated when bit 4 (spie0) of iicc0 is set (to 1).
311 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.6 wait signal (wait) the wait signal (wait) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave devices, the next data transfer can begin. figure 18-13. wait signal (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and acke0 = 1) scl0 6 sda0 78 9 123 scl0 iic0 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock iic0 data write (cancel wait) slave wait after output of eighth clock ffh is written to iic0 or wrel0 is set to 1 transfer lines
312 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-13. wait signal (2/2) (2) when master and slave devices both have a nine-clock wait (master device transmits, slave receives, and acke0 = 1) scl0 6 sda0 789 123 scl0 iic0 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master and slave both wait after output of ninth clock iic0 data write (cancel wait) slave ffh is written to iic0 or wrel0 is set to 1 output accordin g to previousl y set acke0 value transfer lines remarks acke0 : bit 2 of iic control register (iicc0) wrel0 : bit 5 of iic control register (iicc0) a wait may be automatically generated depending on the setting for bit 3 (wtim0) of the iic control register (iicc0). normally, when bit 5 (wrel0) of iicc0 is set to 1 or when ffh is written to the iic shift register (iic0), the wait status is canceled and the transmitting side write data to iic0 to cancel the wait status. the master device can also cancel the wait status via either of the following methods. ? by setting bit 1 (stt0) of iicc0 to 1 ? by setting bit 0 (spt0) of iicc0 to 1
313 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.7 i 2 c interrupt requests (intiic0) the intiic0 interrupt request timing and the iic status register (iics0) settings corresponding to that timing are described below. (1) master device operation (a) start ~ address ~ data ~ data ~ stop (normal transmission/reception) (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 10 110b 2 : iics0 = 10 000b 3 : iics0 = 10 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 10 110b 2 : iics0 = 10 100b 3 : iics0 = 10 00b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
314 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 10 110b 2 : iics0 = 10 000b 3 : iics0 = 10 110b 4 : iics0 = 10 000b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 10 110b 2 : iics0 = 10 00b 3 : iics0 = 10 110b 4 : iics0 = 10 00b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
315 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (c) start ~ code ~ data ~ data ~ stop (extension code transmission) (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1010 110b 2 : iics0 = 1010 000b 3 : iics0 = 1010 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1010 110b 2 : iics0 = 1010 100b 3 : iics0 = 1010 100b 4 : iics0 = 00001001b remark : always generated : generated only when spie0 = 1 : dont care
316 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (2) slave device operation (slave address data reception time (matches with sva0)) (a) start ~ address ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0001 110b 2 : iics0 = 0001 000b 3 : iics0 = 0001 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0001 110b 2 : iics0 = 0001 100b 3 : iics0 = 0001 00b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
317 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches with sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0001 110b 2 : iics0 = 0001 000b 3 : iics0 = 0001 110b 4 : iics0 = 0001 000b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 (after restart, matches with sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0001 110b 2 : iics0 = 0001 00b 3 : iics0 = 0001 110b 4 : iics0 = 0001 00b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
318 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (c) start ~ address ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0001 110b 2 : iics0 = 0001 000b 3 : iics0 = 0010 010b 4 : iics0 = 0010 000b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 6 1 : iics0 = 0001 110b 2 : iics0 = 0001 00b 3 : iics0 = 0010 010b 4 : iics0 = 0010 110b 5 : iics0 = 0010 00b 6 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
319 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (d) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match with address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0001 110b 2 : iics0 = 0001 000b 3 : iics0 = 0000 10b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 (after restart, does not match with address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0001 110b 2 : iics0 = 0001 00b 3 : iics0 = 0000 10b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
320 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (3) slave device operation (when receiving extension code) (a) start ~ code ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0010 010b 2 : iics0 = 0010 000b 3 : iics0 = 0010 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0010 010b 2 : iics0 = 0010 110b 3 : iics0 = 0010 100b 4 : iics0 = 0010 00b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
321 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (b) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches with sva0n) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0010 010b 2 : iics0 = 0010 000b 3 : iics0 = 0001 110b 4 : iics0 = 0001 000b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 (after restart, matches with sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 6 1 : iics0 = 0010 010b 2 : iics0 = 0010 110b 3 : iics0 = 0010 00b 4 : iics0 = 0001 110b 5 : iics0 = 0001 00b 6 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
322 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (c) start ~ code ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0010 010b 2 : iics0 = 0010 000b 3 : iics0 = 0010 010b 4 : iics0 = 0010 000b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 6 7 1 : iics0 = 0010 010b 2 : iics0 = 0010 110b 3 : iics0 = 0010 00b 4 : iics0 = 0010 010b 5 : iics0 = 0010 110b 6 : iics0 = 0010 00b 7 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
323 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (d) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match with address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0010 010b 2 : iics0 = 0010 000b 3 : iics0 = 00000 10b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 (after restart, does not match with address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0010 010b 2 : iics0 = 0010 110b 3 : iics0 = 0010 00b 4 : iics0 = 00000 10b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 1 : iics0 = 00000001b remark : generated only when spie0 = 1
324 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (5) arbitration loss operation (operation as slave after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0101 110b (example: when ald0 is read during interrupt servicing) 2 : iics0 = 0001 000b 3 : iics0 = 0001 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0101 110b (example: when ald0 is read during interrupt servicing) 2 : iics0 = 0001 100b 3 : iics0 = 0001 00b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
325 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (b) when arbitration loss occurs during transmission of extension code (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0110 010b (example: when ald0 is read during interrupt servicing) 2 : iics0 = 0010 000b 3 : iics0 = 0010 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0110 010b (example: when ald0 is read during interrupt servicing) 2 : iics0 = 0010 110b 3 : iics0 = 0010 100b 4 : iics0 = 0010 00b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
326 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (6) operation when arbitration loss occurs (no communication after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 1 : iics0 = 01000110b (example: when ald0 is read during interrupt servicing) 2 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 (b) when arbitration loss occurs during transmission of extension data st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 1 : iics0 = 0110 010b (example: when ald0 is read during interrupt servicing) lrel0 is set to 1 by software 2 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care
327 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (c) when arbitration loss occurs during transmission of data (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 1 : iics0 = 10001110b 2 : iics0 = 01000000b (example: when ald0 is read during interrupt servicing) 3 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 1 : iics0 = 10001110b 2 : iics0 = 01000100b (example: when ald0 is read during interrupt servicing) 3 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1
328 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (d) when loss occurs due to restart condition during data transfer (i) not extension code (example: matches with sva0) st ad6-ad0 rw ak d7-dn st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 1 : iics0 = 1000 110b 2 : iics0 = 01000110b (example: when ald0 is read during interrupt servicing) 3 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care n = 6 - 0 (ii) extension code st ad6-ad0 rw ak d7-dn st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 1 : iics0 = 1000 110b 2 : iics0 = 0110 010b (example: when ald0 is read during interrupt servicing) set iicc0 : lrel0 = 1 3 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care n = 6 - 0
329 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (e) when loss occurs due to stop condition during data transfer st ad6-ad0 rw ak d7-dn sp 1 2 1 : iics0 = 1000 110b 2 : iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : dont care n = 6 - 0 (f) when arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1000 110b 2 : iics0 = 1000 000b 3 : iics0 = 01000000b (example: when ald0 is read during interrupt servicing) 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1000 110b 2 : iics0 = 1000 00b 3 : iics0 = 01000100b (example: when ald0 is read during interrupt servicing) 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care stt0 = 1 ? stt0 = 1 ?
330 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 1 : iics0 = 1000 110b 2 : iics0 = 1000 000b 3 : iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 1 : iics0 = 1000 110b 2 : iics0 = 1000 00b 3 : iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : dont care stt0 = 1 ? stt0 = 1 ?
331 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (h) when arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1000 110b 2 : iics0 = 1000 000b 3 : iics0 = 01000000b (example: when ald0 is read during interrupt servicing) 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1000 110b 2 : iics0 = 1000 00b 3 : iics0 = 01000000b (example: when ald0 is read during interrupt servicing) 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : dont care spt0 = 1 ? spt0 = 1 ?
332 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.8 interrupt request (intiic0) generation timing and wait control the setting of bit 3 (wtim0) in the iic control register (iicc0) determines the timing by which intiic0 is generated and the corresponding wait control, as shown in table 18-2. table 18-2. intiic0 timing and wait control wtim during slave device operation during master device operation address data reception data transmission address data reception data transmission 09 notes 1, 2 8 note 2 8 note 2 988 19 notes 1, 2 9 note 2 9 note 2 999 notes 1. the slave devices intiic0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to the slave address register (sva0). at this point, ack is output regardless of the value set to iicc0s bit 2 (acke0). for a slave device that has received an extension code, intiic0 occurs at the falling edge of the eighth clock. 2. if the received address does not match the contents of the slave address register (sva0), neither intiic0 nor a wait occurs. remark the numbers in the table indicate the number of the serial clocks clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception ? slave device operation : interrupt and wait timing are determined regardless of the wtim0 bit. ? master device operation : interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting bit 5 (wrel0) of iic control register (iicc0) to 1 ? by writing to the iic shift register (iic0) ? by setting a start condition (setting bit 1 (stt0) of iic control register (iicc0) to 1) ? by setting a stop condition (setting iic0s bit 0 (spt0) to 1) when 8-clock wait has been selected (wtim0 = 0), the output level of ack must be determined prior to wait cancellation. (5) stop condition detection intiic0 is generated when a stop condition is detected.
333 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.9 address match detection method when in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match can be detected automatically by hardware. an interrupt frequency (intiic0) occurs when a local address has been set to the slave address register (sva0) and when the address set to sva0 matches the slave address sent by the master device, or when an extension code has been received. 18.5.10 error detection during i 2 c bus mode, the status of the serial data bus (sda0) during data transmission is captured by the iic shift register (iic0) of the transmitting device, so the iic0 data prior to transmission can be compared with the transmitted iic0 data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match. 18.5.11 extension code (1) when the high-order 4 bits of the receive address are either 0000 or 1111, the extension code flag (exc0) is set for extension code reception and an interrupt request (intiic0) is issued at the falling edge of the eighth clock. the local address stored in the slave address register (sva0) is not affected. (2) if 111110 is set to sva0 by a 10-bit address transfer and 111110 0 is transferred from the master device, the results are as follows. note that intiic0 occurs at the falling edge of the eighth clock. ? high-order four bits of data match: exc0 = 1 note ? seven bits of data match: coi0 = 1 note note exc0 : bit 5 of iic status register (iics0) coi0 : bit 4 of iic status register (iics0) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. for example, after the extension code is received, if you do not wish to operate the target device as a slave device, you can set bit 6 (lrel0) of the iic control register (iic0) to 1 to set the standby mode for the next communication operation. table 18-3. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 cbus address 0000 010 address that is reserved for different bus format 1111 0 10-bit slave address specification
334 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.12 arbitration when several master devices simultaneously output a start condition (when stt0 is set to 1 before std0 is set to 1 note ), communication among the master devices is performed as the number of clocks are adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (ald0) in the iic status register (iics0) is set via the timing by which the arbitration loss occurred, and the scl0 and sda0 lines are both set for high impedance, which releases the bus. the arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ald0 = 1 setting that has been made by software. for details of interrupt request timing, see 18.5.7 i 2 c interrupt requests (intiic0) . note std0 : bit 1 of iic status register (iics0) stt0 : bit 1 of iic control register (iicc0) figure 18-14. arbitration timing example master 1 master 2 transfer lines scl0 sda0 scl0 sda0 scl0 sda0 master 1 loses arbitration hi-z hi-z
335 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) table 18-4. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission at falling edge of eighth or ninth clock following byte transfer note 1 read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data transmission when restart condition is detected during data transfer when stop condition is detected during data transfer when stop condition is output (when spie0 = 1) note 2 when data is at low level while attempting to output a at falling edge of eighth or ninth clock following byte transfer note 1 restart condition when stop condition is detected while attempting to when stop condition is output (when spie0 = 1) note 2 output a restart condition when data is at low level while attempting to output a at falling edge of eighth or ninth clock following byte transfer note 1 stop condition when scl0 is at low level while attempting to output a restart condition notes 1. when wtim0 (bit 3 of the iic control register iicc0) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim0 = 0 and the extension codes slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a chance that arbitration will occur, set spie0 = 1 for master device operation. remark spie0 : bit 5 of the iic control register (iicc0) 18.5.13 wake up function the i 2 c bus slave function is a function that generates an interrupt request (intiic0) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wake-up standby mode is set. this wake-up standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, bit 5 (spie0) of the iic control register (iicc0) is set regardless of the wake up function, and this determines whether interrupt requests are enabled or prohibited.
336 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.14 communication reservation to start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of the iic control register (iicc0) was set to 1). if bit 1 (stt0) of iicc0 is set while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait status is set. when the bus release is detected (when a stop condition is detected), writing to the iic shift register (iic0) causes the masters address transfer to start. at this point, iicc0s bit 4 (spie0) should be set. when stt0 has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status. ? if the bus has been released ........................................... a start condition is generated ? if the bus has not been released (standby mode) .......... communication reservation check whether the communication reservation operates or not with msts0 (bit 7 of the iic status register (iics0)) after sst0 is set and a wait time elapses. wait periods, which should be set via software, are listed in table 18-5. these wait periods can be set via the settings for bits 3 and 0 (smc0 and cl00) in the iic clock select register (iiccl0). table 18-5. wait periods smc0 cl00 wait period 0 0 26 clocks 0 1 46 clocks 1 0 16 clocks 11 figure 18-5 shows communication reservation timing.
337 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-15. communication reservation timing 2 1 3456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iic0 set spd0 and intiic0 stt0 =1 communication reservation set std0 output b y master with bus access remark iic0 : iic shift register stt0 : bit 1 of iic control register (iicc0) std0 : bit 1 of iic status register (iics0) spd0 : bit 0 of iic status register (iics0) communication reservations are accepted via the following timing. after bit 1 (std0) of the iic status register (iics0) is set to 1, a communication reservation can be made by setting bit 1 (stt0) of the iic control register (iicc0) to 1 before a stop condition is detected. figure 18-16. timing for accepting communication reservations scl0 sda0 std0 spd0 standb y mode figure 18-17 shows the communication reservation protocol.
338 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-17. communication reservation protocol note the communication reservation operation executes a write to the iic shift register (iic0) when a stop condition interrupt request occurs. remark stt0 : bit 1 of iic control register (iicc0) msts0 : bit 7 of iic status register (iics0) iic0 : iic shift register 18.5.15 other cautions after a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. (a) set iic clock select register (iiccl0). (b) set bit 7 (iice0) of the iic control register (iicc0). (c) set bit 0 of iicc0. di set1 stt0 define communication reservation wait cancel communication reservation no yes mov iic0, # h ei msts0 = 0? (communication reservation) note (generate start condition) sets stt0 flag (communication reservation) gets wait period set by software (see table 18-5). confirmation of communicatin reservation clear user flag iic0 write operation defines that communication reservation is in effect (defines and sets user flag to any part of ram)
339 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.5.16 communication operations (1) master operations the following is a flow chart of the master operations. figure 18-18. master operation flow chart iiccl0 h select transfer clock iicc0 h iice0=spie0=wtim0=1 stt0=1 start iic0 write transfer start iic0 write transfer wrel0=1 start reception generate stop condition (no slave with matching address) generate restart condition or stop condition start data processing data processing acke0=0? no yes no no no no no no yes yes yes yes yes intiic0=1? wtim0=0 acke0=1 intiic0=1? transfer completed? intiic0=1? ackd0=1? trc0=1? intiic0=1? ackd0=1? stop condition detection address transfer completion no (receive) yes (transmit)
340 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) (2) slave operation an example of slave operation is shown below. figure 18-19. slave operation flow chart iicc0 h iice0=1 wrel0=1 start reception detect restart condition or stop condition start acke0=0 data processing data processing lrel0=1 no yes no no no no no no no yes no yes yes yes yes yes yes wtim0=0 acke0=1 intiic0=1? yes communicate? transfer completed? intiic0=1? wtim0=1 start iic0 write transfer intiic0=1? exc0=1? coi0=1? trc0=1? ackd0=1 ?
341 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) 18.6 timing charts when using the i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the trc0 bit (bit 3 of the iic status register (iics0)) that specifies the data transfer direction and then starts serial communication with the slave device. figures 18-20 and 18-21 show timing charts of the data communication. the iic bus shift register (iic0)s shift operation is synchronized with the falling edge of the serial clock (scl0). the transmit data is transferred to the so0 latch and is output (msb first) via the sda0 pin. data input via the sda0 pin is captured into iic0 at the rising edge of scl0.
342 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-20. example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (1) start condition ~ address note to cancel slave wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 3 2 1 a6 a5 a4 a3 a2 a1 a0 w ack d4 d5 d6 d7 iic0 address iic0 data iic0 ffh transmit start condition receive (when exc0 = 1) note note
343 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-20. example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (2) data iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0 data iic0 ffh note iic0 ffh note iic0 data transmit receive note note note to cancel slave wait, write ffh to iic0 or set wrel0.
344 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-20. example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (3) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 a5 a6 iic0 data iic0 address iic0 ffh note iic0 ffh note stop condition start condition transmit note note (when spie0 = 1) receive (when spie0 = 1) note to cancel slave wait, write ffh to iic0 or set wrel0.
345 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-21. example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (1) start condition ~ address note to cancel slave wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h l l h h l acke0 msts0 stt0 l l spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 a6 a5 a4 a3 a2 a1 a0 r d4 d3 d2 d5 d6 d7 iic0 address iic0 ffh note note iic0 data start condition
346 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-21. example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (2) data iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0 data iic0 data iic0 ffh note iic0 ffh note note to cancel slave wait, write ffh to iic0 or set wrel0.
347 chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) figure 18-21. example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (3) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l h h acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 a5 a6 iic0 address iic0 ffh note note iic0 data stop condition start condition (when spie0 = 1) n - ack (when spie0 = 1) note to cancel slave wait, write ffh to iic0 or set wrel0.
348 [memo]
349 chapter 19 interrupt functions 19.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. it does not undergo priority control and is given top priority over all other interrupt requests. it generates a standby release signal. one interrupt from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag registers (pr0l, pr0h, pr1l). multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (see table 19-1 ). a standby release signal is generated. five external interrupts request and thirteen internal interrupts request are incorporated as maskable interrupts. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in a disabled stated. the software interrupt does not undergo interrupt priority control. 19.2 interrupt sources and configuration a total of 20 interrupt sources exist among non-maskable, maskable, and software interrupts (see table 19-1 ).
350 chapter 19 interrupt functions table 19-1. interrupt source list default interrupt source internal/ vector basic interrupt external table configuration type priority note 1 name trigger address type note 2 non- intwdt watchdog timer overflow internal 0004h (a) maskable (with watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intser0 serial interface uart0 reception error internal 000eh (b) generation 6 intsr0 end of serial interface uart0 reception 0010h 7 intst0 end of serial interface uart0 transmission 0012h 8 intcsi30 end of serial interface sio3 (sio30) transfer 0014h 9 intcsi31 end of serial interface sio3 (sio31) transfer 0016h [only for m pd780024, 780034 subseries] 10 intiic0 end of serial interface iic0 transfer 0018h [only for m pd780024y, 780034y subseries] 11 intwti reference time interval signal from watch timer 001ah 12 inttm00 generation of 16-bit timer register and 001ch capture/compare register 00 (cr00) match signal (with cr00 specified to compare register) 13 inttm01 generation of 16-bit timer register and 001eh capture/compare register 01 (cr01) match signal (with cr01 specified to compare register 14 inttm50 generation of 8-bit timer/event counter 50 0020h match signal 15 inttm51 generation of 8-bit timer/event counter 51 0022h coincidence signal 16 intad0 end of a/d converter conversion 0024h 17 intwt watch timer overflow 0026h 18 intkr port 4 falling edge detection external 0028h (d) software brk brk instruction execution 003eh (e) notes 1. the default priority is the priority applicable when two or more maskable interrupt are generated simultaneously. 0 is the highest priority, and 18 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 19-1.
351 chapter 19 interrupt functions figure 19-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt internal bus interrupt request priority control circuit vector table address generator standby release signal (b) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority control circuit vector table address generator standby release signal (c) external maskable interrupt (intp0 to intp3) internal bus interrupt request if mk ie pr isp priority control circuit vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector
352 chapter 19 interrupt functions figure 19-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (intkr) if mk ie pr isp internal bus interrupt request priority control circuit vector table address generator standby release signal falling edge detector (e) software interrupt internal bus interrupt request priority control circuit vector table address generator if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specify flag
353 chapter 19 interrupt functions 19.3 interrupt function control registers the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag register (if0l, if0h, if1l) ? interrupt mask flag register (mk0l, mk0h, mk1l) ? priority specify flag register (pr0l, pr0h, pr1l) ? external interrupt rising edge enable flag (egp) ? external interrupt falling edge enable flag (egn) ? program status word (psw) table 19-2 gives a list of interrupt request flags, interrupt mask flags, and priority specify flags corresponding to interrupt request sources. table 19-2. flags corresponding to interrupt request sources interrupt request interrupt request flag interrupt mask flag priority specify flag register register register intwdt wdtif if0l wdtmk mk0l wdtpr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intser0 serif0 sermk0 serpr0 intsr0 srif0 srmk0 srpr0 intst0 stif0 stmk0 stpr0 intcsi30 csiif30 if0h csimk30 mk0h csipr30 pr0h intcsi31 note 1 csiif31 note 1 csimk31 note 1 csipr31 note 1 intiic0 note 2 iicif0 note 2 iicmk0 note 2 iicpr note 2 intwti wtiif wtimk wtipr inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 inttm50 tmif50 tmmk50 tmpr50 inttm51 tmif51 tmmk51 tmpr51 intad0 adif0 if1l admk0 mk1l adpr0 pr1l intwt wtif wtmk wtpr intkr krif krmk krpr notes 1. m pd780024, 780034 subseries only 2. m pd780024y, 780034y subseries only
354 chapter 19 interrupt functions (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, and if1l are set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h are combined to form 16-bit register if0, they are read with a 16-bit memory manipulation instruction. reset input sets these registers to 00h. figure 19-2. interrupt request flag register (if0l, if0h, if1l) format address: ffe0h after reset: 00h r/w symbol 76543210 if0l stif0 srif0 serif0 pif3 pif2 pif1 pif0 wdtif address: ffe1h after reset: 00h r/w symbol 76543210 if0h tmif51 tmif50 tmif01 tmif00 wtiif iicif0 note 1 csiif31 note 2 csiif30 address: ffe2h after reset: 00h r/w symbol 76543210 if1l 00000 krif wtif adif0 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status notes 1. incorporated only in the m pd780024 and 780034 subseries. be sure to set 0 for the m pd780024y, 780034y subseries. 2. incorporated only in the m pd780024y, 780034y subseries. be sure to set 0 for the m pd780024, 780034 subseries. cautions 1. the wdtif flag is r/w enabled only when the watchdog timer is used as the interval timer. if watchdog timer mode 1 is used, set the wdtif flag to 0. 2. be sure to set 0 to if1l bits 3 to 7. 3. when operating a timer, serial interface, or a/d converter after stand-by release, run it once after clearing an interrupt request flag. an interrupt request flag may be set by noise.
355 chapter 19 interrupt functions (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. mk0l, mk0h, and mk1l are set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h are combined to form a 16-bit register, they are set with a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 19-3. interrupt mask flag register (mk0l, mk0h, mk1l) format address: ffe4h after reset: ffh r/w symbol 7 6 5 43210 mk0l stmk0 srmk0 sermk0 pmk3 pmk2 pmk1 pmk0 wdtmk address: ffe5h after reset: ffh r/w symbol 7 6 5 43210 mk0h tmmk51 tmmk50 tmmk01 tmmk00 wtimk iicmk0 note 1 csimk31 note 2 csimk30 address: ffe6h after reset: ffh r/w symbol 7 6 5 43210 mk1l 1 1 1 1 1 krmk wtmk admk0 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. incorporated only in the m pd780024 and 780034 subseries. be sure to set 1 for the m pd780024y, 780034y subseries. 2. incorporated only in the m pd780024y, 780034y subseries. be sure to set 1 for the m pd780024, 780034 subseries. cautions 1. if the watchdog timer is used in watchdog timer mode 1, the contents of the wdtmk flag become undefined when read. 2. because port 0 pins have an alternate function as external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. always set mk1l bits 3 to 7 to 1.
356 chapter 19 interrupt functions (3) priority specify flag registers (pr0l, pr0h, pr1l) the priority specify flag registers are used to set the corresponding maskable interrupt priority orders. pr0l, pr0h, and pr1l are set by a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are combined to form 16-bit register pr0, they are set with a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 19-4. priority specify flag register (pr0l, pr0h, pr1l) format address: ffe8h after reset: ffh r/w symbol 76543210 pr0l stpr0 srpr0 serpr0 ppr3 ppr2 ppr1 ppr0 wdtpr address: ffe9h after reset: ffh r/w symbol 76543210 pr0h tmpr51 tmpr50 tmpr01 tmpr00 wtipr iicpr0 note 1 csipr31 note 2 csipr30 address: ffeah after reset: ffh r/w symbol 76543210 pr1l 11111 krpr wtpr adpr0 xxprx priority level selection 0 high priority level 1 low priority level notes 1. incorporated only in the m pd780024 and 780034 subseries. be sure to set 1 for the m pd780024y, 780034y subseries. 2. incorporated only in the m pd780024y, 780034y subseries. be sure to set 1 for the m pd780024, 780034 subseries. cautions 1. when the watchdog timer is used in the watchdog timer 1 mode, set 1 in the wdtpr flag. 2. always set pr1l bits 3 to 7 to 1.
357 chapter 19 interrupt functions (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp3. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. figure 19-5. external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) format address: ff48h after reset: 00h r/w symbol 7 6 5 43210 egp 0 0 0 0 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 43210 egn 0 0 0 0 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 3) 0 0 interrupt disable 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges
358 chapter 19 interrupt functions (5) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for an interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control multiple processing are mapped. besides 8-bit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, if the brk instruction is executed, the contents of psw are automatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specify flag of the acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with the push psw instruction. they are reset from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 19-6. program status word format 7 ie 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disable) ie 0 1 disable priority of interrupt currently being serviced interrupt request acknowledge enable/disable used when normal instruction is executed enable interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enable) 0 1
359 chapter 19 interrupt functions 19.4 interrupt servicing operations 19.4.1 non-maskable interrupt request acknowledge operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. it does not undergo interrupt priority control and has highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag and isp flag are reset (0), and the contents of the vector table are loaded into pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction is executed. however, if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one non- maskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program execution. figures 19-7, 19-8, and 19-9 show the flowchart of the non-maskable interrupt request generation through acknowledge, acknowledge timing of non-maskable interrupt request, and acknowledge operation at multiple non- maskable interrupt request generation, respectively.
360 chapter 19 interrupt functions figure 19-7. non-maskable interrupt request generation to acknowledge flowchart start wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdt interrupt servicing? interrupt control register not accessed? interval timer no reset processing no interrupt request generation start of interrupt servicing interrupt request held pending no no no yes yes yes yes yes wdtm: watchdog timer mode register wdt : watchdog timer wdtm3 = 0 (with non-maskable interrupt selected)? figure 19-8. non-maskable interrupt request acknowledge timing instruction instruction psw, pc save, jump to interrupt servicing interrupt service progam cpu processing wdtif interrupt request generated during this interval is acknowledged at . wdtif: watchdog timer interrupt request flag
361 chapter 19 interrupt functions figure 19-9. non-maskable interrupt request acknowledge operation (a) if a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution main routine nmi request <1> execution of 1 instruction nmi request <2> execution of nmi request <1> nmi request <2> held pending servicing of nmi request <2> that was pended (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request <1> execution of 1 instruction execution of nmi request <1> nmi request <2> held pending nmi request <3> held pending servicing of nmi request <2> that was pended nmi request <3> not acknowledged (although two or more nmi requests have been generated, onl y one re q uest is acknowled g ed. nmi request <2> nmi request <3>
362 chapter 19 interrupt functions 19.4.2 maskable interrupt acknowledge operation a maskable interrupt becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if in the interrupt enable state (when ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until interrupt servicing is performed are listed in table 19-3 below. for the interrupt request acknowledge timing, see figures 19-11 and 19-12. table 19-3. times from generation of maskable interrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specify flag is acknowledged first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is acknowledged when it becomes acknowledgeable. figure 19-10 shows the interrupt request acknowledge algorithm. if a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the priority specify flag corresponding to the acknowledged interrupt are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into pc and branched. return from an interrupt is possible with the reti instruction.
363 chapter 19 interrupt functions figure 19-10. interrupt request acknowledge processing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if : interrupt request flag mk : interrupt mask flag pr : priority specify flag ie : flag that controls acknowledge of maskable interrupt request (1 = enable, 0 = disable) isp : flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request received, or low-priority interrupt servicing)
364 chapter 19 interrupt functions figure 19-11. interrupt request acknowledge timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 19-12. interrupt request acknowledge timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 19.4.3 software interrupt request acknowledge operation a software interrupt acknowledge is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vector table (003eh, 003fh) are loaded into pc and branched. return from a software interrupt is possible with the retb instruction. caution do not use the reti instruction for returning from the software interrupt.
365 chapter 19 interrupt functions 19.4.4 multiple interrupt servicing multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt. multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (ie = 1) (except non-maskable interrupts). also, when an interrupt request is received, interrupt requests acknowledge becomes disabled (ie = 0). therefore, to enable multiple interrupts, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledge. moreover, even if interrupts are enabled, multiple interrupts may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupts. in the interrupt enable state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held pending. when servicing of the current interrupt ends, the pended interrupt request is acknowledged following execution of one main processing instruction execution. multiple interrupt servicing is not possible during non-maskable interrupt servicing. table 19-4 shows interrupt requests enabled for multiple interrupt servicing, and figure 19-13 shows multiple interrupt examples. table 19-4. interrupt request enabled for multiple interrupt during interrupt servicing multiple interrupt request maskable interrupt request non-maskable interrupt request pr = 0 pr = 1 interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt maskable interrupt isp = 0 isp = 1 software interrupt remarks 1. : multiple interrupt enable 2. : multiple interrupt disable 3. isp and ie are flags contained in psw. isp = 0 : an interrupt with higher priority is being serviced. isp = 1 : no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0 : interrupt request acknowledge is disabled. ie = 1 : interrupt request acknowledge is enabled. 4. pr is a flag contained in pr0l, pr0h, and pr1l. pr = 0 : higher priority level pr = 1 : lower priority level
366 chapter 19 interrupt functions figure 19-13. multiple interrupt examples (1/2) example 1. multiple interrupts occur twice during servicing of interrupt intxx, two interrupt requests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledge. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0 : higher priority level pr = 1 : lower priority level ie = 0 : interrupt request acknowledge disable main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0
367 chapter 19 interrupt functions figure 19-13. multiple interrupt examples (2/2) example 3. multiple interrupt servicing does not occur because interrupt is not enabled interrupt is not enabled during servicing of interrupt intxx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0 : higher priority level ie = 0 : interrupt request acknowledge disabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0
368 chapter 19 interrupt functions 19.4.5 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. these instructions (interrupt request hold instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw. bit, cy ? mov1 cy, psw. bit ? and1 cy, psw. bit ? or1 cy, psw. bit ? xor1 cy, psw. bit ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? push psw ? pop psw ? bt psw. bit, $addr16 ? bf psw. bit, $addr16 ? btclr psw. bit, $addr16 ?ei ?di ? manipulate instructions for the if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, egp, and egn registers. caution the brk instruction is not one of the above-listed interrupt request hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt requests is generated during execution of the brk instruction, the interrupt request is not acknowledged. however, a non-maskable interrupt request is acknowledged. figure 19-14 shows the timing with which interrupt requests are held pending. figure 19-14. interrupt request hold instruction n instruction m save psw and pc, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other than interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (instruction request)
369 chapter 20 external device expansion function 20.1 external device expansion function the external device expansion function connects external devices to areas other than the internal rom, ram, and sfr. connection of external devices uses ports 4 to 6. ports 4 to 6 control address/data, read/write strobe, wait, address strobe, etc. table 20-1. pin functions in external memory expansion mode pin function at external device connection alternate function name function ad0 to ad7 multiplexed address/data bus p40 to p47 a8 to a15 address bus p50 to p57 rd read strobe signal p64 wr write strobe signal p65 wait wait signal p66 astb address strobe signal p67 table 20-2. state of port 4 to 6 pins in external memory expansion mode port port 4 port 5 port 6 external expansion mode 0 to 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 single-chip mode port port port 256-byte expansion mode address/data port port rd, wr, wait, astb 4-kbyte expansion mode address/data address port port rd, wr, wait, astb 16-kbyte expansion mode address/data address port port rd, wr, wait, astb full-address mode address/data address port rd, wr, wait, astb caution when the external wait function is not used, the wait pin can be used as a port in all modes.
370 chapter 20 external device expansion function the memory maps when the external device expansion function is used are as follows. figure 20-1. memory map when using external device function (1/2) (a) memory map of m pd780021, 780031, 780021y, 780031y and of m pd78f0034, 78f0034y when internal rom (flash memory) size is 8 kbytes (b) memory map of m pd780022, 780032, 780022y, 780032y and of m pd78f0034, 78f0034y when internal rom (flash memory) size is 16 kbytes sfr internal high-speed ram reserved full-address mode (when mm2 - mm0 = 111) 16-kbyte expansion mode (when mm2 - mm0 = 101) 4-kbyte expansion mode (when mm2 - mm0 = 100) 256-byte expansion mode (when mm2 - mm0 = 011) single-chip mode ffffh ff00h feffh fd00h fcffh f800h f7ffh 6000h 5fffh 3000h 2fffh 2100h 20ffh 2000h 1fffh 0000h ffffh ff00h feffh fd00h fcffh f800h f7ffh 8000h 7fffh 5000h 4fffh 4100h 40ffh 4000h 3fffh 0000h sfr internal high-speed ram reserved full-address mode (when mm2 - mm0 = 111) 16-kbyte expansion mode (when mm2 - mm0 = 101) 4-kbyte expansion mode (when mm2 - mm0 = 100) 256-byte expansion mode (when mm2 - mm0 = 011) single-chip mode
371 chapter 20 external device expansion function figure 20-1. memory map when using external device function (2/2) (c) memory map of m pd780023, 780033, 780023y, 780033y and of m pd78f0034, 78f0034y when internal rom (flash memory) size is 24 kbytes (d) memory map of m pd780024, 780034, 780024y, 780034y and of m pd78f0034, 780034y when in- ternal rom (flash memory) size is 32 kbytes sfr internal high-speed ram reserved full-address mode (when mm2 - mm0 = 111) 16-kbyte expansion mode (when mm2 - mm0 = 101) 256-byte expansion mode (when mm2 - mm0 = 011) single-chip mode ffffh ff00h feffh fb00h faffh f800h f7ffh a000h 9fffh 6100h 60ffh 0000h 7000h 6fffh 6000h 5fffh 4-kbyte expansion mode (when mm2 - mm0 = 100) ffffh ff00h feffh fb00h faffh f800h f7ffh c000h bfffh 8100h 80ffh 0000h 9000h 8fffh 8000h 7fffh sfr internal high-speed ram reserved full-address mode (when mm2 - mm0 = 111) 16-kbyte expansion mode (when mm2 - mm0 = 101) 256-byte expansion mode (when mm2 - mm0 = 011) single-chip mode 4-kbyte expansion mode (when mm2 - mm0 = 100)
372 chapter 20 external device expansion function 20.2 external device expansion function control register the external device expansion function is controlled by the following two types of registers. ? memory expansion mode register (mem) ? memory expansion wait setting register (mm) (1) memory expansion mode register (mem) mem sets the external expansion area. mem is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets mem to 00h. figure 20-2. memory expansion mode register (mem) format address: ff47h after reset: 00h r/w symbol 76543210 mem 00000mm2mm1mm0 mm2 mm1 mm0 single-chip/memory p40 to p47, p50 to p57, p64 to p67 pin state expansion mode selection p40 to p47 p50 to p53 p54, p55 p56, p57 p64 to p67 0 0 0 single-chip mode port mode 001 0 1 1 memory 256-byte ad0 to ad7 port mode p64 = rd expansion mode p65 = wr 100 mode 4-kbyte a8 to a11 port mode p66 =wait mode p67 = astb 1 0 1 16-kbyte a12, a13 port mode mode 111 full-address a14, a15 mode note other than above setting prohibited note the full-address mode allows external expansion to the entire 64-kbyte address space except for the internal rom, ram, sfr areas and the reserved areas.
373 chapter 20 external device expansion function (2) memory expansion wait setting register (mm) mm sets the number of waits. mm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets mm to 10h. figure 20-3. memory expansion wait setting register (mm) format address: fff8h after reset: 10h r/w symbol 7 6 5 43210 mm 00pw1pw00000 pw1 pw0 wait control 0 0 no wait 0 1 wait (one wait state inserted) 1 0 setting prohibited 1 1 wait control by external wait pin
374 chapter 20 external device expansion function 20.3 external device expansion function timing timing control signal output pins in the external memory expansion mode are as follows. (1) rd pin (alternate function: p64) read strobe output pin. the read strobe output pin is output in data accesses and instruction fetches from external memory. during internal memory access, the read strobe signal is not output (maintains high level). (2) wr pin (alternate function: p65) write strobe signal output pin. the write strobe signal is output in data access to external memory. during internal memory access, the write strobe signal is not output (maintains high level) (3) wait pin (alternate function: p66) external wait signal input pin. when the external wait is not used, the wait pin can be used as an input/output port. during internal memory access, the external wait signal is ignored. (4) astb pin (alternate function: p67) address strobe signal output pin. the address strobe signal is output regardless of data access and instruction fetch from external memory. during internal memory access, the address strobe signal is not output. (5) ad0 to ad7, a8 to a15 pins (alternate function: p40 to p47, p50 to p57) address/data signal output pins. valid signal is output or input during data accesses and instruction fetches from external memory. these signals change even during internal memory access (output values are undefined). the timing charts are shown in figures 20-4 to 20-7.
375 chapter 20 external device expansion function figure 20-4. instruction fetch from external memory (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 lower address instruction code higher address rd astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address instruction code higher address rd astb ad0 to ad7 a8 to a15 wait lower address instruction code higher address
376 chapter 20 external device expansion function figure 20-5. external memory read timing (a) no wait (pw1, pw0 = 0, 0) setting rd astb ad0 to ad7 a8 to a15 lower address read data higher address (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 wait lower address read data higher address rd astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address read data higher address
377 chapter 20 external device expansion function figure 20-6. external memory write timing (a) no wait (pw1, pw0 = 0, 0) setting wr astb ad0 to ad7 a8 to a15 lower address write data higher address hi-z (b) wait (pw1, pw0 = 0, 1) setting wr astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address write data higher address hi-z (c) external wait (pw1, pw0 = 1, 1) setting wr astb ad0 to ad7 a8 to a15 wait lower address write data higher address hi-z
378 chapter 20 external device expansion function figure 20-7. external memory read modify write timing (a) no wait (pw1, pw0 = 0, 0) setting read data write data higher address hi-z lower address rd astb ad0 to ad7 a8 to a15 wr (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting wait hi-z rd astb ad0 to ad7 a8 to a15 wr write data higher address read data lower address rd astb ad0 to ad7 a8 to a15 hi-z wr write data higher address internal wait signal (1-clock wait) read data lower address
379 chapter 20 external device expansion function 20.4 example of connection with memory this section provide an example of connecting the m pd780024 with external memory (in this example, sram) in figure 20-8. in addition, the external device expansion function is used in the full-address mode, and the addresses from 0000h to 7fffh (32 kbytes) are allocated for internal rom, and the addresses after 8000h from sram. figure 20-8. connection example of m pd780024 and memory rd wr a8 to a14 astb ad0 to ad7 v dd0 pd74hc573 le d0 to d7 oe q0 to q7 pd43256b cs oe we i/o1 to i/o8 a0 to a14 data bus pd780024 address bus m m m
380 [memo]
381 chapter 21 standby function 21.1 standby function and configuration 21.1.1 standby function the standby function is designed to decrease power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. the system clock oscillator continues oscillating. in this mode, current consumption is not decreased as much as in the stop mode. however, the halt mode is effective to restart operation immediately upon interrupt request and to carry out intermittent operations such as watch applications. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops, stopping the whole system, thereby considerably reducing the cpu power consumption. data memory low-voltage hold (down to v dd = 1.6 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is required to secure an oscillation stabilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. in either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. the input/output port output latch and output buffer statuses are also held. cautions 1. the stop mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). the halt mode can be used with either the main system clock or the subsystem clock. 2. when operation is transferred to the stop mode, be sure to stop the peripheral hardware operation and execute the stop instruction. 3. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs0) of the a/d converter mode register (adm0) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction.
382 chapter 21 standby function 21.1.2 standby function control register the wait time after the stop mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. figure 21-1. oscillation stabilization time select register (osts) format address: fffah after reset: 04h r/w symbol 76543210 osts 00000 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time 0002 12 /f x (488 m s) 0012 14 /f x (1.95 ms) 0102 15 /f x (3.91 ms) 0112 16 /f x (7.81 ms) 1002 17 /f x (15.6 ms) other than above setting prohibited caution the wait time after the stop mode is cleared does not include the time (see "a" in the illustration below) from stop mode clear to clock oscillation start. the time is not included either by reset input or by interrupt request generation. stop mode clear x1 pin voltage waveform v ss a remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz.
383 chapter 21 standby function 21.2 standby function operations 21.2.1 halt mode (1) halt mode setting and operating statuses the halt mode is set by executing the halt instruction. it can be set with the main system clock or the subsystem clock. the operating statuses in the halt mode are described below. table 21-1. halt mode operating statuses halt mode during halt instruction execution during halt instruction execution setting using main system clock using subsystem clock without subsystem with subsystem with main system with main system item clock note 1 clock note 2 clock oscillation clock oscillation stopped clock generator both main system clock and subsystem clock can be oscillated. clock supply to cpu stops. cpu operation stops. port (output latch) status before halt mode setting is held. 16-bit timer/event operable operable when ti00 counter is selected. 8-bit timer/event operable operable when ti50, counter ti51 are selected as count clock. watch timer operable when f x /2 7 is operable operable when f xt is selected as count clock selected as count clock. watchdog timer operable operation stops. a/d converter stop serial interface operable operable during external sck. external interrupt operable bus line ad0 to ad7 high impedance during a8 to a15 status before halt mode setting is held. external astb low level expansion wr, rd high level wait high impedance notes 1. including case when external clock is not supplied. 2. including case when external clock is supplied.
384 chapter 21 standby function (2) halt mode clear the halt mode can be cleared with the following three types of sources. (a) clear upon unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is cleared. if interrupt acknowledge is enabled, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 21-2. halt mode clear upon interrupt request generation halt instruction wait wait operation mode halt mode operation mode oscillation clock standby release signal interrupt request remarks 1. the broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged. 2. wait times are as follows: ? when vectored interrupt service is carried out : 8 or 9 clocks ? when vectored interrupt service is not carried out : 2 or 3 clocks (b) clear upon non-maskable interrupt request when an non-maskable interrupt request is generated, the halt mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled.
385 chapter 21 standby function (c) clear upon reset input when reset signal is input, halt mode is released. and, as in the case with normal reset operation, a program is executed after branch to the reset vector address. figure 21-3. halt mode release by reset input halt instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode halt mode operating mode oscillation stop clock reset signal oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz. table 21-2. operation after halt mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt service execution 1 halt mode hold non-maskable interrupt request interrupt service execution reset input reset processing : dont care
386 chapter 21 standby function 21.2.2 stop mode (1) stop mode setting and operating status the stop mode is set by executing the stop instruction. it can be set only with the main system clock. cautions 1. when the stop mode is set, the x2 pin is internally connected to v dd1 via a pull-up resistor to minimize the leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait set using the oscillation stabilization time select register (osts), the operating mode is set. the operating status in the stop mode is described in table 21-3 below. table 21-3. stop mode operating status stop mode setting with subsystem clock without subsystem clock item clock generator only main system clock oscillation is stopped. cpu operation stops. port (output latch) status before stop mode setting is held. 16-bit timer/event counter operation stops. 8-bit timer/event counter operable only when ti50, ti51 are selected as count clock. watch timer operable when f xt is selected as operation stops. counter clock. watchdog timer operation stops. clock output/buzzer output pcl and buz at low level. a/d converter operation stops serial interface other than uart operable only when externally supplied clock is specified as the serial clock. uart operation stops. (transmit shift register (txs0), receive shift register (rx0), and receive buffer register (rxb0) hold the value just before the clock stop.) external interrupt operatable bus line during ad0 to ad7 high impedance external expansion a8 to a15 status before stop mode setting is held. astb low level wr, rd high level wait high impedance
387 chapter 21 standby function (2) stop mode release the stop mode can be released by the following two types of sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. if interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 21-4. stop mode release by interrupt request generation stop instruction wait (time set by osts) oscillation stabilization wait status operating mode stop mode operating mode oscillation clock standby release signal oscillation stop oscillation interrupt request remark the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged.
388 chapter 21 standby function (b) release by reset input the stop mode is cleared when reset signal is input, and after the lapse of oscillation stabilization time, reset operation is carried out. figure 21-5. stop mode release by reset input stop instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode stop mode operating mode oscillation stop clock reset signal oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz. table 21-4. operation after stop mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt service execution 1 stop mode hold reset input reset processing : dont care
389 chapter 22 reset function 22.1 reset function the following two operations are available to generate the reset function. (1) external reset input via reset pin (2) internal reset by watchdog timer runaway time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in table 22-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset pin, the reset is cleared and program execution starts after the lapse of oscillation stabilization time 2 17 /f x . the reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 2 17 /f x (see figures 22-2 to 22-4). cautions 1. for an external reset, input a low level for 10 m s or more to the reset pin. 2. during reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pin becomes high-impedance. figure 22-1. reset function block diagram reset count clock reset control circuit watchdog timer stop overflow reset signal interrupt function
390 chapter 22 reset function figure 22-2. timing of reset by reset input delay delay hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin figure 22-3. timing of reset due to watchdog timer overflow hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 watchdog timer overflow internal reset signal port pin figure 22-4. timing of reset in stop mode by reset input delay delay hi-z normal operation oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin stop status (oscillation stop) stop instruction execution reset period (oscillation stop)
391 chapter 22 reset function table 22-1. hardware statuses after reset (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general register undefined note 2 port (output latch) 00h port mode registers (pm0, pm2 to pm7) ffh pull-up resistor option registers (pu0, pu2 to pu7) 00h processor clock control register (pcc) 04h memory size switching register (ims) cfh note 3 memory expansion mode register (mem) 00h memory expansion wait setting register (mm) 10h oscillation stabilization time selection register (osts) 04h 16-bit timer/event timer register (tm0) 00h counter capture/compare register (cr00, cr01) undefined prescaler mode register (prm0) 00h mode control register (tmc0) 00h output control register (toc0) 00h 8-bit timer/event counter timer counters (tm50, tm51) 00h compare registers (cr50, cr51) undefined clock selection registers (tcl50, tcl51) 00h mode control register (tmc50, tmc51) 04h watch timer mode control register (wtm) 00h watchdog timer clock selection register (wdcs) 00h mode register (wdtm) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. although the initial value is cfh, use the following value to be set for each version. m pd780021, 780021y, 780031, 780031y : 42h m pd780022, 780022y, 780032, 780032y : 44h m pd780023, 780023y, 780033, 780033y : c6h m pd780024, 780024y, 780034, 780034y : c8h m pd78f0034, 78f0034y : value for mask rom versions
392 chapter 22 reset function table 22-1. hardware statuses after reset (2/2) hardware status after reset clock output/buzzer output controller clock output selection register (cks) 00h a/d converter conversion result registers (adcr0) 00h mode register (adm0) 00h analog input channel specification register (ads0) 00h serial interface (uart0) asynchronous serial interface mode register (asim0) 00h asynchronous serial interface status register (asis0) 00h baud rate generator control register (brgc0) 00h transmit shift register (txs0) ffh receive buffer register (rxb0) serial interface (sio3) shift registers (sio30, sio31 note 1 ) undefined operating mode registers (csim30, csim31 note 1 ) 00h serial interface (iic0) note 2 clock selection register (iiccl0) 00h shift register (iic0) 00h control register (iicc0) 00h status register (iics0) 00h slave address register (sva0) 00h interrupt request flag registers (if0l, if0h, if1l) 00h mask flag registers (mk0l, mk0h, mk1l) ffh priority specify flag registers (pr0l, pr0h, pr1l) ffh external interrupt rising edge enable register (egp) 00h external interrupt falling edge enable register (egn) 00h notes 1. provided only in the m pd780024, 780034 subseries. 2. provided only in the m pd780024y, 780034y subseries.
393 chapter 23 m pd78f0034, 78f0034y the m pd78f0034 and 78f0034y are provided as the flash memory versions of the m pd780024, 780024y, 780034, 780034y subseries. for purposes of simplification, throughout this chapter, the m pd78f0034 is used to refer to both the m pd78f0034 and 78f0034y. in the same way, with regard to mask rom versions, the m pd78f0034 is used to refer to the m pd780021, 780022, 780023, 780024 and the m pd780031, 780032, 780033, 780034, respectively. the m pd78f0034s replace the internal mask rom of the m pd780034 with flash memory to which a program can be written, deleted and overwritten while mounted on the substrate. table 23-1 lists the differences among the m pd78f0034 and the mask rom versions.
394 chapter 23 m pd78f0034, 78f0034y table 23-1. differences among m pd78f0034 and mask rom versions item m pd78f0034 mask rom versions internal rom configuration flash memory mask rom internal rom capacity 32 kbytes m pd780021, 780031: 8 kbytes m pd780022, 780032: 16 kbytes m pd780023, 780033: 24 kbytes m pd780024, 780034: 32 kbytes internal high-speed ram capacity 1024 bytes m pd780021, 780031: 512 bytes m pd780022, 780032: 512 bytes m pd780023, 780033: 1024 bytes m pd780024, 780034: 1024 bytes change of internal rom and internal possible note not provided high-speed ram capacity using memory size switching register ic pin none available v pp pin available none electrical specifications refer to data sheet of each product. note reset input causes the flash memory and internal high-speed ram capacities to become 32 kbytes and 1024 bytes, respectively. caution flash memory versions and mask rom versions differ in their noise immunity and noise radiation. if replacing flash memory versions with mask rom versions when changing from test production to mass production, be sure to perform sufficient evaluation with cs versions (not es versions) of mask rom versions.
395 chapter 23 m pd78f0034, 78f0034y 23.1 memory size switching register the m pd78f0034 allows users to select the internal memory capacity using the memory size switching register (ims) so that the same memory map as that of the m pd780021, 780022, 780023, 780024 and m pd780031, 780032, 780033, 780034 with a different size of internal memory capacity can be achieved. ims is set by using an 8-bit memory manipulation instruction. reset input sets ims to cfh. figure 23-1. memory size switching register (ims) format address: fff0h after reset: cfh w symbol 7 6 5 43210 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal high-speed ram capacity selection 0 1 0 512 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 0 0 1 0 8 kbytes 0 1 0 0 16 kbytes 0 1 1 0 24 kbytes 1 0 0 0 32 kbytes 1 1 1 1 60 kbytes (setting prohibited) other than above setting prohibited the ims settings to obtain the same memory map as mask rom versions are shown in table 23-2. table 23-2. memory size switching register settings target mask rom versions ims setting m pd780021, 780031 42h m pd780022, 780032 44h m pd780023, 780033 c6h m pd780024, 780034 c8h caution when using the mask rom versions, be sure to set the value indicated in table 23-2 to ims.
396 chapter 23 m pd78f0034, 78f0034y 23.2 flash memory programming on-board writing of flash memory (with device mounted on target system) is supported. on-board writing is done after connecting a dedicated flash programmer (flashpro ii (type fl-pr2)) to the host machine and target system. moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to flashpro ii. remark flashpro ii is a product of naitou densei machidaseisakusho co., ltd. 23.2.1 selection of transmission method writing to flash memory is performed using flashpro ii and serial communication. select the transmission method for writing from table 23-3. for the selection of the transmission method, a format like the one shown in figure 23-2 is used. the transmission methods are selected with the v pp pulse numbers shown in table 23-3. table 23-3. transmission method list transmission method number of channels pin used number of v pp pulses 3-wire serial i/o 1 si30/p20 0 so30/p21 sck30/p22 3-wire serial i/o 1 si31/p34 1 ( m pd78f0034 only) so31/p35 sck31/p36 uart 1 rxd0/p23 8 txd0/p24 asck0/p25 i 2 c bus 1 sda0/p32 4 ( m pd78f0034y only) scl0/p33 pseudo 3-wire serial i/o 1 p72/ti50/to50 12 (serial clock input) p71/ti01 (serial data output) p70/ti00/to0 (serial data input) cautions 1. be sure to select the number of v pp pulses shown in table 23-3 for the transmission method. 2. if performing write operations to flash memory with the uart transmission method, set the main system clock oscillation frequency to 3 mhz or higher. figure 23-2. transmission method selection format 10 v v pp reset v dd v ss v dd v ss v pp pulses flash memory write mode
397 chapter 23 m pd78f0034, 78f0034y 23.2.2 flash memory programming function flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. the main functions are listed in table 23-4. table 23-4. main functions of flash memory programming function description reset used to detect write stop and transmission synchronization. batch verify compares entire memory contents and input data. batch delete deletes the entire memory contents. batch blank check checks the deletion status of the entire memory. high-speed write performs writing to flash memory according to write start address and number of write data (bytes). continuous write performs successive write operations using the data input with high-speed write operation. status checks the current operation mode and operation end. oscillation frequency setting inputs the resonator oscillation frequency information. delete time setting inputs the memory delete time. baud rate setting sets the transmission rate when the uart method is used. i 2 c mode setting sets the standard/high-speed mode when the i 2 c bus method is used. silicon signature read outputs the device name, memory capacity, and device block information. 23.2.3 flashpro ii connection connection of the flashpro ii and the m pd78f0034 differs depending on communication method (3-wire serial i/ o, uart, and i 2 c bus). each type of connection is shown in figures 23-3, 23-4, and 23-5. figure 23-3. connection of flashpro ii using 3-wire serial i/o method v pp v dd reset sck so si gnd v pp v dd reset sck3n si3n so3n v ss flashpro ii pd78f0034 m n = 0, 1
398 chapter 23 m pd78f0034, 78f0034y figure 23-4. flashpro ii connection using uart method v pp v dd reset so si gnd v pp v dd reset rxd0 txd0 v ss flashpro ii pd78f0034 m figure 23-5. flashpro ii connection using i 2 c bus method v pp v dd reset sck si gnd v pp v dd reset scl0 sda0 v ss flashpro ii pd78f0034y m figure 23-6. flashpro ii connection using pseudo 3-wire serial i/o v pp v dd reset sck so si gnd v pp v dd reset p72 (serial clock input) p70 (serial data input) p71 (serial data output) v ss flashpro ii pd78f0034 m
399 chapter 24 instruction set this chapter lists each instruction set of the m pd780024, 780034, 780024y, 780034y subseries in table form. for details of its operation and operation code, refer to the separate document 78k/0 series users manual instructions (u12326e) .
400 chapter 24 instruction set 24.1 legends used in operation list 24.1.1 operand identifiers and description methods operands are described in operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. each symbol has the following meaning. ? # : immediate data specification ? ! : absolute address specification ? $ : relative address specification ? [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 24-1. operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even address only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special-function register symbols, refer to table 5-5 special-function register list .
401 chapter 24 instruction set 24.1.2 description of operation column a : a register; 8-bit accumulator x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag rbs : register bank select flag ie : interrupt request enable flag nmis : non-maskable interrupt servicing flag ( ) : memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 24.1.3 description of flag operation column (blank) : not affected 0 : cleared to 0 1 : set to 1 : set/cleared according to the result r : previously saved value is restored
402 chapter 24 instruction set 24.2 operation list clock flag note 1 note 2 zaccy mov r, #byte 2 4 C r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 C 7 sfr byte a, r note 3 12 Ca r r, a note 3 12 Cr a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 C 5 a sfr sfr, a 2 C 5 sfr a a, !addr16 3 8 9 + n a (addr16) !addr16, a 3 8 9 + m (addr16) a psw, #byte 3 C 7 psw byte a, psw 2 C 5 a psw psw, a 2 C 5 psw a a, [de] 1 4 5 + n a (de) [de], a 1 4 5 + m (de) a a, [hl] 1 4 5 + n a (hl) [hl], a 1 4 5 + m (hl) a a, [hl + byte] 2 8 9 + n a (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) a a, [hl + b] 1 6 7 + n a (hl + b) [hl + b], a 1 6 7 + m (hl + b) a a, [hl + c] 1 6 7 + n a (hl + c) [hl + c], a 1 6 7 + m (hl + c) a xch a, r note 3 12 Ca r a, saddr 2 4 6 a (saddr) a, sfr 2 C 6 a (sfr) a, !addr16 3 8 10 + n + m a (addr16) a, [de] 1 4 6 + n + m a (de) a, [hl] 1 4 6 + n + m a (hl) a, [hl + byte] 2 8 10 + n + m a (hl + byte) a, [hl + b] 2 8 10 + n + m a (hl + b) a, [hl + c] 2 8 10 + n + m a (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group 8-bit data transfer
403 chapter 24 instruction set clock flag note 1 note 2 zaccy movw rp, #word 3 6 C rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 C 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 C 8 ax sfrp sfrp, ax 2 C 8 sfrp ax ax, rp note 3 1 4 C ax rp rp, ax note 3 1 4 C rp ax ax, !addr16 3 10 12 + 2n ax (addr16) !addr16, ax 3 10 12 + 2m (addr16) ax xchw ax, rp note 3 1 4 C ax rp add a, #byte 2 4 C a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 C a, cy a + r r, a 2 4 C r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 + n a, cy a + (addr16) a, [hl] 1 4 5 + n a, cy a + (hl) a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) a, [hl + b] 2 8 9 + n a, cy a + (hl + b) a, [hl + c] 2 8 9 + n a, cy a + (hl + c) addc a, #byte 2 4 C a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 C a, cy a + r + cy r, a 2 4 C r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 + n a, cy a + (addr16) + cy a, [hl] 1 4 5 + n a, cy a + (hl) + cy a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 + n a, cy a + (hl + b) + cy a, [hl + c] 2 8 9 + n a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group 16-bit data transfer 8-bit operation
404 chapter 24 instruction set clock flag note 1 note 2 zaccy sub a, #byte 2 4 C a, cy a C byte saddr, #byte 3 6 8 (saddr), cy (saddr) C byte a, r note 3 2 4 C a, cy a C r r, a 2 4 C r, cy r C a a, saddr 2 4 5 a, cy a C (saddr) a, !addr16 3 8 9 + n a, cy a C (addr16) a, [hl] 1 4 5 + n a, cy a C (hl) a, [hl + byte] 2 8 9 + n a, cy a C (hl + byte) a, [hl + b] 2 8 9 + n a, cy a C (hl + b) a, [hl + c] 2 8 9 + n a, cy a C (hl + c) subc a, #byte 2 4 C a, cy a C byte C cy saddr, #byte 3 6 8 (saddr), cy (saddr) C byte C cy a, r note 3 2 4 C a, cy a C r C cy r, a 2 4 C r, cy r C a C cy a, saddr 2 4 5 a, cy a C (saddr) C cy a, !addr16 3 8 9 + n a, cy a C (addr16) C cy a, [hl] 1 4 5 + n a, cy a C (hl) C cy a, [hl + byte] 2 8 9 + n a, cy a C (hl + byte) C cy a, [hl + b] 2 8 9 + n a, cy a C (hl + b) C cy a, [hl + c] 2 8 9 + n a, cy a C (hl + c) C cy and a, #byte 2 4 C a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 Ca a r r, a 2 4 C r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a [hl] a, [hl + byte] 2 8 9 + n a a [hl + byte] a, [hl + b] 2 8 9 + n a a [hl + b] a, [hl + c] 2 8 9 + n a a [hl + c] notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. mnemonic operands byte operation instruction group 8-bit operation
405 chapter 24 instruction set clock flag note 1 note 2 zaccy or a, #byte 2 4 C a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 Ca a r r, a 2 4 C r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) xor a, #byte 2 4 C a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 Ca a r r, a 2 4 C r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) cmp a, #byte 2 4 C a C byte saddr, #byte 3 6 8 (saddr) C byte a, r note 3 24 Ca C r r, a 2 4 C r C a a, saddr 2 4 5 a C (saddr) a, !addr16 3 8 9 + n a C (addr16) a, [hl] 1 4 5 + n a C (hl) a, [hl + byte] 2 8 9 + n a C (hl + byte) a, [hl + b] 2 8 9 + n a C (hl + b) a, [hl + c] 2 8 9 + n a C (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. mnemonic operands byte operation instruction group 8-bit operation
406 chapter 24 instruction set clock flag note 1 note 2 zaccy addw ax, #word 3 6 C ax, cy ax + word subw ax, #word 3 6 C ax, cy ax C word cmpw ax, #word 3 6 C ax C word mulu x 2 16 C ax a x divuw c 2 25 C ax (quotient), c (remainder) ax c inc r12Cr r + 1 saddr 2 4 6 (saddr) (saddr) + 1 dec r12Cr r C 1 saddr 2 4 6 (saddr) (saddr) C 1 incw rp 1 4 C rp rp + 1 decw rp 1 4 C rp rp C 1 ror a, 1 1 2 C (cy, a 7 a 0 , a m C 1 a m ) 1 time rol a, 1 1 2 C (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 C (cy a 0 , a 7 cy, a m C 1 a m ) 1 time rolc a, 1 1 2 C (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 + n + m a 3 C 0 (hl) 3 C 0 , (hl) 7 C 4 a 3 C 0 , (hl) 3 C 0 (hl) 7 C 4 rol4 [hl] 2 10 12 + n + m a 3 C 0 (hl) 7 C 4 , (hl) 3 C 0 a 3 C 0 , (hl) 7 C 4 (hl) 3 C 0 adjba 2 4 C decimal adjust accumulator after addition adjbs 2 4 C decimal adjust accumulator after subtract mov1 cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 C 7 cy sfr.bit cy, a.bit 2 4 C cy a.bit cy, psw.bit 3 C 7 cy psw.bit cy, [hl].bit 2 6 7 + n cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 C 8 sfr.bit cy a.bit, cy 2 4 C a.bit cy psw.bit, cy 3 C 8 psw.bit cy [hl].bit, cy 2 6 8 + n + m (hl).bit cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group 16-bit operation increment/ decrement bcd adjust bit manipu- late multiply/ divide rotate
407 chapter 24 instruction set clock flag note 1 note 2 zaccy and1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 C 7 cy cy sfr.bit cy, a.bit 2 4 C cy cy a.bit cy, psw.bit 3 C 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit or1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 C 7 cy cy sfr.bit cy, a.bit 2 4 C cy cy a.bit cy, psw.bit 3 C 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit xor1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 C 7 cy cy sfr.bit cy, a.bit 2 4 C cy cy a.bit cy, psw. bit 3 C 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit set1 saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 C 8 sfr.bit 1 a.bit 2 4 C a.bit 1 psw.bit 2 C 6 psw.bit 1 [hl].bit 2 6 8 + n + m (hl).bit 1 clr1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 C 8 sfr.bit 0 a.bit 2 4 C a.bit 0 psw.bit 2 C 6 psw.bit 0 [hl].bit 2 6 8 + n + m (hl).bit 0 set1 cy 1 2 C cy 11 clr1 cy 1 2 C cy 00 not1 cy 1 2 C cy cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group bit manipu- late
408 chapter 24 instruction set uncondi- tional branch stack manipu- late conditional branch call/return clock flag note 1 note 2 zaccy call !addr16 3 7 C (sp C 1) (pc + 3) h , (sp C 2) (pc + 3) l , pc addr16, sp sp C 2 callf !addr11 2 5 C (sp C 1) (pc + 2) h , (sp C 2) (pc + 2) l , pc 15 C 11 00001, pc 10 C 0 addr11, sp sp C 2 callt [addr5] 1 6 C (sp C 1) (pc + 1) h , (sp C 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp C 2 brk 1 6 C (sp C 1) psw, (sp C 2) (pc + 1) h , (sp C 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp C 3, ie 0 ret 16 Cpc h (sp + 1), pc l (sp), sp sp + 2 reti 16 Cpc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3, nmis 0 retb 16 Cpc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3 push psw 1 2 C (sp C 1) psw, sp sp C 1 rp 1 4 C (sp C 1) rp h , (sp C 2) rp l , sp sp C 2 pop psw 1 2 C psw (sp), sp sp + 1 r r r rp 1 4 C rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, #word 4 C 10 sp word sp, ax 2 C 8 sp ax ax, sp 2 C 8 ax sp br !addr16 3 6 C pc addr16 $addr16 2 6 C pc pc + 2 + jdisp8 ax 2 8 C pc h a, pc l x bc $addr16 2 6 C pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 C pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 C pc pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 C pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. mnemonic operands byte operation instruction group
409 chapter 24 instruction set clock flag note 1 note 2 zaccy bt saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 C 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 C pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 C 9 pc pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 C 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 C pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 C 11 pc pc + 4 + jdisp8 if psw. bit = 0 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 0 btclr saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) sfr.bit, $addr16 4 C 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 C pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 C 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr16 3 10 12 + n + m pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b, $addr16 2 6 C b b C 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 C c c C1, then pc pc + 2 + jdisp8 if c 0 saddr. $addr16 3 8 10 (saddr) (saddr) C 1, then pc pc + 3 + jdisp8 if(saddr) 0 sel rbn 2 4 C rbs1, 0 n nop 1 2 C no operation ei 2 C 6 ie 1(enable interrupt) di 2 C 6 ie 0(disable interrupt) halt 2 6 C set halt mode stop 2 6 C set stop mode notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group cpu control condi- tional branch
410 chapter 24 instruction set 24.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz
411 chapter 24 instruction set second operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none first operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a
412 chapter 24 instruction set (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand #word ax rp note sfrp saddrp !addr16 sp none first operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1
413 chapter 24 instruction set (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand ax !addr16 !addr11 [addr5] $addr16 first operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
414 [memo]
415 appendix a differences between m pd78014h, 78018f, 780024, and 780034 subseries table a-1 shows the major differences between m pd78014h, 78018f, 780024, and 780034 subseries. table a-1. major differences between m pd78014h, 78018f, 780024, and 780034 subseries name m pd78014h subseries m pd78018f subseries m pd780024, 780034 items subseries anti-emi noise measure provided none provided internal i 2 c bus version none exist exist (multimaster (y subseries) supported) prom (flash memory) version m pd78p018f m pd78f0034 power supply voltage v dd = 1.8 to 5.5 v internal high-speed ram size 512 bytes 512 bytes 512 bytes m pd78011h, 78012h m pd78011f, 78012f m pd780021/31 1024 bytes 1024 bytes m pd780022/32 m pd78013h, 78014h m pd78013f, 78014f 1024 bytes m pd78015f, 78016f m pd780023/33 m pd78018f m pd780024/34 internal expansion ram size none 512 bytes none m pd78015f, 78016f 1024 bytes m pd78018f min. instruction execution time 0.4 m s (10 mhz) 0.24 m s (8.38 mhz) number of i/o port 53 51 a/d converter 8 bits 8 8 bits 8 10 bits 8 ( m pd780034 subseries) operation subseries other 3-wire/2-wire/sbi: 1 3-wire : 2, uart: 1 mode of than y series 3-wire (automatic transmit and receive): 1 serial y subseries 3-wire/2-wire/i 2 c: 1 3-wire : 1, uart: 1, interface 3-wire (automatic multimaster i 2 c: 1 transmit and receive): 1 package ? 64-pin plastic shrink dip (750 mils) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic ? 64-pin ceramic shrink ? 64-pin plastic lqfp (12 12 mm) dip (with window) lqfp (12 12 mm) (750 mils) note ? 64-pin ceramic wqfn (14 14 mm) note programmer adapter pa-78p018cw, pa-78p018gc, the development tool pa-78p018gk, pa-78p018kk-s system differs from other emulation board ie-78014-r-em-a subseries. electric specifications refer to the data sheet of each product. recommended soldering conditions note only for prom version
416 [memo]
417 appendix b development tools the following development tools are available for the development of systems that employ the m pd780024, 780034, 780024y, and 780034y subseries. figure b-1 shows the development tool configuration. figure b-1. development tool configuration (1/2) (1) when using the in-circuit emulator ie-78k0-ns ?system simulator ?integrated debugger ?device file embedded software ?real-time os ?os debugging tool ?assembler package ?c compiler package ?c library source file ?device file language processing software flash memory write adapter in-circuit emulator power supply unit emulation probe conversion socket or conversion adapter target system host machine (pc) interface adapter, pc card interface, etc. emulation board on-chip flash memory version flash memory write environment flash programmer
418 appendix b development tools figure b-1. development tool configuration (2/2) (2) when using the in-circuit emulator ie-78001-r-a remark items in broken line boxes differ according to the development environment. refer to b.3.1. hardware . ?system simulator ?integrated debugger ?device file embedded software ?real-time os ?os debugging tool ?assembler package ?c compiler package ?c library source file ?device file language processing software flash memory write adapter in-circuit emulator emulation probe conversion socket or conversion adapter target system host machine (pc or ews) interface board interface adapter emulation board i/o board probe board emulation probe conversion board on-chip flash memory version flash memory write environment flash programmer
419 appendix b development tools b.1 language processing software ra78k/0 assembler package cc78k/0 c compiler package df780024 note df780034 note device file cc78k/0-l c library source file note the df780024 and df780034 can be used in common with the ra78k/0, cc78k/0, sm78k0, id78k0-ns, and id78k0. this assembler converts programs written in mnemonics into an object codes executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with an optical device file (df780024 or df780034). this assembler package is a dos-based application. it can also be used in win- dows, however, by using the project manager (included in assembler package) on windows. part number: m s ra78k0 this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler should be used in combination with an optical assembler package and device file. this c compiler package is a dos-based application. it can also be used in win- dows, however, by using the project manager (included in assembler package) on windows. part number: m s cc78k0 this file contains information peculiar to the device. this device file should be used in combination with an optical tool (ra78k/0, cc78k/0, sm78k0, id78k0-ns, and id78k0). corresponding os and host machine differ depending on the tool to be used with. ? df780024: for m pd780024, 780024y subseries ? df780034: for m pd780034, 780034y subseries part number: m s df780024, m s df780034 this is a source file of functions configuring the object library included in the c compiler package (cc78k/0). this file is required to match the object library included in c compiler package to the customers specifications. part number: m s cc78k0-l
420 appendix b development tools remark in the part number differs depending on the host machine and os used. m s ra78k0 m s cc78k0 m s df780024 m s df780034 m s cc78k0-l host machine os supply medium aa13 pc-9800 series windows (japanese version) notes 1, 2 3.5-inch 2hd fd ab13 ibm pc/at tm and its compatibles windows (japanese version) notes 1, 2 3.5-inch 2hc fd bb13 windows (english version) notes 1, 2 3p16 hp9000 series 700 tm hp-ux tm (rel. 9.05) dat (dds) 3k13 sparcstation tm sunos tm (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news tm (risc) news-os tm (rel. 6.1) 3.5-inch 2hc fd notes 1. can be operated in dos environment. 2. not support windowsnt tm b.2 flash memory writing tools flashpro ii (type fl-pr2) flash programmer fa-64cw fa-64gc fa-64gk note flash memory writing adapter note under development. remark flashpro ii, fa-64cw, fa-64gc, and fa-64gk are products of naito densei machidaseisakusho co., ltd. phone: (044) 822-3813 naitou densei machidaseisakusho co., ltd. flash programmer dedicated to microcontrollers with on-chip flash memory. flash memory writing adapter used connected to the flashpro ii. ? fa-64cw : 64-pin plastic shrink dip (cw type) ? fa-64gc : 64-pin plastic qfp (gc-ab8 type) ? fa-64gk : 64-pin plastic lqfp (gk-8a8 type)
421 appendix b development tools b.3 debugging tools b.3.1 hardware (1/2) (1) when using the in-circuit emulator ie-78k0-ns ie-78k0-ns note in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c note interface adapter ie-70000-cd-if note pc card interface ie-70000-pc-if-c note interface adapter ie-780034-ns-em1 note emulation board np-64cw emulation probe np-64gc emulation probe ev-9200gc-64 conversion socket (refer to figures b-2 and b-3 ) np-64gk emulation probe tgk-064sbw conversion adapter (refer to figure b-4 ) note under development remarks 1. np-64cw, np-64gc, and np-64gk are products of naitou densei machidaseisakusho co., ltd. phone: (044) 822-3813 naitou densei machidaseisakusho co., ltd. 2. tgk-064sbw is a product of tokyo eletech corporation. phone: (03) 3820-7112 tokyo electronic component division (06) 244-6672 osaka electronic component division 3. ev-9200gc-64 is sold in five units. 4. tgk-064sbw is sold in one units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to integrated debugger (id78k0-ns). this emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. this adapter is used for supplying power from a receptacle of 100-v to 240-v ac. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-78k0-ns host machine. this is pc card and interface cable required when using the pc-9800 series notebook-type computer as the ie-78k0-ns host machine. this adapter is required when using the ibm pc and its compatible computers as the ie-78k0-ns host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator to the target system and is designed for 64-pin plastic shrink dip (cw type). this probe is used to connect the in-circuit emulator to the target system and is designed for 64-pin plastic qfp (gc-ab8 type). this conversion socket connects the np-64gc to the target system board designed to mount a 64-pin plastic qfp (gc-ab8 type). this probe is used to connect the in-circuit emulator to the target system and is designed for 64-pin plastic lqfp (gk-8a8 type). this conversion socket connects the np-64gk to the target system board designed to mount a 64-pin plastic lqfp (gk-8a8 type).
422 appendix b development tools b.3.1 hardware (2/2) (2) when using the in-circuit emulator ie-78001-r-a ie-78001-r-a note in-circuit emulator ie-70000-98-if-b or ie-7000-98-if-c note interface adapter ie-70000-pc-if-b or ie-7000-pc-if-c note interface adapter ie-78000-r-sv3 interface adapter ie-780034-ns-em1 note emulation board ie-78k0-r-ex1 note emulation probe conversion board ep-78240cw-r emulation probe ep-78240gc-r emulation probe ev-9200gc-64 conversion socket (refer to figures b-2 and b-3 ) ep-78012gk-r emulation probe tgk-064sbw conversion adapter (refer to figure b-4 ) note under development remarks 1. tgk-064sbw is a product of tokyo eletech corporation. phone: (03) 3820-7112 tokyo electronic component division (06) 244-6672 osaka electronic component division 2. ev-9200gc-64 is sold in five units. 3. tgk-064sbw is sold in one units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to integrated debugger (id78k0). this emulator should be used in combination with emulation probe and interface adapter, which is required to connect this emulator to the host machine. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-78001-r-a host machine. this adapter is required when using the ibm pc/at and its compatible computers as the ie-78001-r-a host machine. this is adapter and cable required when using an ews computer as the ie-78001- r-a host machine, and is used connected to the board in the ie-78000-r-a. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator and emulation conver- sion board. this board is required when using the ie-780034-ns-em1 on the ie-78001-r-a. this probe is used to connect the in-circuit emulator to the target system and is designed for 64-pin plastic shrink dip (cw type). this probe is used to connect the in-circuit emulator to the target system and is designed for 64-pin plastic qfp (gc-ab8 type). this conversion socket connects the ep-78240gc-r to the target system board designed to mount a 64-pin plastic qfp (gc-ab8 type). this probe is used to connect the in-circuit emulator to the target system and is designed for 64-pin plastic lqfp (gk-8a8 type). this conversion socket connects the ep-78012gk-r to the target system board designed to mount a 64-pin plastic lqfp (gk-8a8 type).
423 appendix b development tools b.3.2 software (1/2) sm78k0 this system simulator is used to perform debugging at c source level or assembler system simulator level while simulating the operation of the target system on a host machine. this simulator runs on windows. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with the optical device file (df780024 or df780034). part number: m s sm78k0 remark in the part number differs depending on the host machine and os used. m s sm78k0 host machine os supply medium aa13 pc-9800 series windows (japanese version) note 3.5-inch 2hd fd ab13 ibm pc/at and its compatibles windows (japanese version) note 3.5-inch 2hc fd bb13 windows (english version) note note not support windowsnt
424 appendix b development tools b.3.2 software (2/2) id78k0-ns note integrated debugger (supporting in-circuit emulator ie-78k0-ns) id78k0 integrated debugger (supporting in-circuit emulator ie-78001-r-a) note under development remark in the part number differs depending on the host machine and os used. m s id78k0-ns host machine os supply medium aa13 pc-9800 series windows (japanese version) note 3.5-inch 2hd fd ab13 ibm pc/at and its compatibles windows (japanese version) note 3.5-inch 2hc fd bb13 windows (english version) note note not support windowsnt m s id78k0 host machine os supply medium aa13 pc-9800 series windows (japanese version) note 3.5-inch 2hd fd ab13 ibm pc/at and its compatibles windows (japanese version) note 3.5-inch 2hc fd bb13 windows (english version) note 3p16 hp9000 series 700 hp-ux (rel. 9.05) dat (dds) 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news tm (risc) news-os (rel. 6.1) 3.5-inch 2hc fd note not support windowsnt this debugger is a control program to debug 78k/0 series microcontrollers. it adopts a graphical user interface, which is equivalent visually and operationally to windows or osf/motif?. it also has an enhanced debugging function for c language programs, and thus trace results can be displayed on screen in c-language level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. in addition, by incorporating function modules such as task debugger and system performance analyzer, the efficiency of debugging programs, which run on real-time oss can be improved. it should be used in combination with the optional device file. part number: m s id78k0-ns, m s id78k0
425 appendix b development tools b.4 system upgrade from former in-circuit emulator for 78k/0 series to ie-78001-r-a if you already have a former in-circuit emulator for 78k/0 series microcontrollers (ie-78000-r or ie-78000-r-a), that in-circuit emulator can operate as an equivalent to the ie-78001-r-a by replacing its internal break board with the ie-78001-r-bk (under development). table b-1. system-up method from former in-circuit emulator for 78k/0 series to the ie-78001-r-a in-circuit emulator owned in-circuit emulator cabinet system-up note board to be purchased ie-78000-r required ie-78001-r-bk ie-78000-r-a not required note for system-up of a cabinet, send your in-circuit emulator to nec.
426 appendix b development tools conversion socket drawing (ev-9200gc-64) and footprints figure b-2. ev-9200gc-64 drawing (for reference only) a f 1 e ev-9200gc-64 b d c m n l k r q i h p o s t j g no.1 pin index ev-9200gc-64-g0 item millimeters inches a b c d e f g h i j k l m n o p q r s t 18.8 14.1 14.1 18.8 4-c 3.0 0.8 6.0 15.8 18.5 6.0 15.8 18.5 8.0 7.8 2.5 2.0 1.35 0.35 0.1 2.3 1.5 0.74 0.555 0.555 0.74 4-c 0.118 0.031 0.236 0.622 0.728 0.236 0.622 0.728 0.315 0.307 0.098 0.079 0.053 0.014 0.091 0.059 +0.004 ?.005 f f f f
427 appendix b development tools figure b-3. ev-9200gc-64 footprints (for reference only) f e d g h i j k l c b a 0.031 0.591=0.472 0.031 0.591=0.472 ev-9200gc-64-p1e item millimeters inches a b c d e f g h i j k l 19.5 14.8 14.8 19.5 6.00 0.08 6.00 0.08 0.5 0.02 2.36 0.03 2.2 0.1 1.57 0.03 0.768 0.583 0.583 0.768 0.236 0.236 0.197 0.093 0.087 0.062 0.8 0.02 15=12.0 0.05 0.8 0.02 15=12.0 0.05 f f f +0.002 ?.001 +0.003 ?.002 +0.002 ?.001 +0.003 ?.002 +0.004 ?.003 +0.004 ?.003 +0.001 ?.002 f f f +0.001 ?.002 +0.004 ?.005 +0.001 ?.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution
428 appendix b development tools conversion adapter drawing (tgk-064sbw) figure b-4. tgk-064sbw drawing (for reference only) item millimeters inches b 1.85 0.073 c 3.5 0.138 a 0.3 0.012 d 2.0 0.079 h 5.9 0.232 i 0.8 0.031 j 2.4 0.094 e 3.9 0.154 f 1.325 g 1.325 0.052 0.052 item millimeters inches b 0.65x15=9.75 0.026x0.591=0.384 c 0.65 0.026 a 18.4 0.724 d h 0.65x15=9.75 0.026x0.591=0.384 i 11.85 0.467 j 18.4 0.724 e 10.15 0.400 f 12.55 0.494 k c 2.0 c 0.079 l 12.45 0.490 m q 11.1 0.437 r 1.45 0.057 s 1.45 0.057 n 7.7 0.303 o 10.02 p 14.92 0.587 0.394 w 5.3 0.209 x 4-c 1.0 4-c 0.039 y 3.55 0.140 t 4- 1.3 4- 0.051 u 1.8 v 5.0 0.197 0.071 z 0.9 0.035 7.75 10.25 0.305 0.404 g 14.95 0.589 f f f f f f f f k 2.7 0.106 tgk-064sbw-g0e ff h a h a g z c l q n b c i j k g f e d m x r s w o p protrusion height u t v k j i y e d b f note : product by tokyo eletech corporation.
429 appendix c embedded software for efficient development and maintenance of the m pd780024, 780024y, 780034, and 780034y subseries, the following embedded products are available.
430 appendix c embedded software real-time os (1/2) rx78k/0 rx 78k/0 is a real-time os conforming to the m itron specifications. real-time os tool (configurator) for generating nucleus of rx78k/0 and plural information tables is supplied. used in combination with an optional assembler package (ra78/0) and device file (df780024 or df780034). the real-time os is a dos-based application. it should be used in the dos prompt when using in windows. part number: m s rx78013- dddd caution when purchasing the rx78k/0, fill in the purchase application form in advance and sign the user agreement. remark and dddd in the part number differ depending on the host machine and os used. m s rx78013- dddd dddd product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k mass-production object 0.1 million units 001m 1 million units 010m 10 million units s01 source program source program for mass-produced object host machine os supply medium aa13 pc-9800 series windows (japanese version) notes 1, 2 3.5-inch 2hd fd ab13 ibm pc/at and its compatibles windows (japanese version) notes 1, 2 3.5-inch 2hc fd bb13 windows (english version) notes 1, 2 3p16 hp9000 series 700 hp-ux (rel. 9.05) dat (dds) 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news (risc) news-os (rel. 6.1) 3.5-inch 2hc fd notes 1. can also be operated in dos environment. 2. not support windowsnt.
431 appendix c embedded software real-time os (2/2) mx78k0 mx78k/0 is an os for m itron specification subsets. a nucleus for the mx78k/0 is os also included as a companion product. this manages tasks, events, and time. in the task management, determining the task execution order and switching from task to the next task are performed. the mx78k/0 is a dos-based application. it should be used in the dos prompt when using in windows. part number: m s mx78k0- ddd remark and ddd in the part number differ depending on the host machine and os used. m s mx78k0- ddd ddd product outline maximum number for use in mass production 001 evaluation object use in preproduction stages. mass-production object use in mass production stages. s01 source program only the users who purchased mass-production objects are allowed to purchase this program. host machine os supply medium aa13 pc-9800 series windows (japanese version) notes 1, 2 3.5-inch 2hd fd ab13 ibm pc/at and its compatibles windows (japanese version) notes 1, 2 3.5-inch 2hc fd bb13 windows (english version) notes 1, 2 3p16 hp9000 series 700 hp-ux (rel. 9.05) dat (dds) 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news (risc) news-os (rel. 6.1) 3.5-inch 2hc fd notes 1. can also be operated in dos environment. 2. not support windowsnt.
432 [memo]
433 appendix d register index d.1 register index (in alphabetical order with respect to register names) [a] a/d conversion result register 0 (adcr0) 230, 245 a/d converter mode register (adm0) 232, 249 analog input channel specification register (ads0) 234, 251 asynchronous serial interface mode register (asim0) 265, 269 asynchronous serial interface status register (asis0) 267, 271 [b] baud rate generator control register (brgc0) 267, 272 [c] capture/compare control register (crc0) 164 capture/compare register 00 (cr00) 161 capture/compare register 01 (cr01) 162 clock output selection register (cks) 224 [e] 8-bit compare register 50 (cr50) 191 8-bit compare register 51 (cr51) 191 8-bit counter 50 (tm50) 191 8-bit counter 51 (tm51) 191 8-bit timer mode control register 50 (tmc50) 193 8-bit timer mode control register 51 (tmc51) 193 external interrupt falling edge enable register (egn) 235, 251, 357 external interrupt rising edge enable register (egp) 235, 251, 357 [i] iic clock select register (iiccl0) 304 iic control register (iicc0) 297 iic shift register (iic0) 296, 303 iic status register (iics0) 301 interrupt mask flag register 0h (mk0h) 355 interrupt mask flag register 0l (mk0l) 355 interrupt mask flag register 1l (mk1l) 355 interrupt request flag register 0h (if0h) 354 interrupt request flag register 0l (if0l) 354 interrupt request flag register 1l (if1l) 354 [m] memory expansion wait setting register (mm) 373 memory size switching register (ims) 395 memory expansion mode register (mem) 372
434 appendix d register index [o] oscillation stabilization time select register (osts) 382 [p] port 0 (p0) 124 port 1 (p1) 125 port 2 (p2) 126 port 3 (p3) 127, 129 port 4 (p4) 132 port 5 (p5) 133 port 6 (p6) 134 port 7 (p7) 135 port mode register 0 (pm0) 136 port mode register 2 (pm2) 136 port mode register 3 (pm3) 136 port mode register 4 (pm4) 136 port mode register 5 (pm5) 136 port mode register 6 (pm6) 136 port mode register 7 (pm7) 136, 167, 195, 226 prescaler mode register (prm0) 166 priority specify flag register 0h (pr0h) 356 priority specify flag register 0l (pr0l) 356 priority specify flag register 1l (pr1l) 356 processor clock control register (pcc) 146 program status word (psw) 100, 358 pull-up resistor option register 0 (pu0) 138 pull-up resistor option register 2 (pu2) 138 pull-up resistor option register 3 (pu3) 138 pull-up resistor option register 4 (pu4) 138 pull-up resistor option register 5 (pu5) 138 pull-up resistor option register 6 (pu6) 138 pull-up resistor option register 7 (pu7) 138 [r] receive buffer register (rxb0) 264 receive shift register (rxs0) 264 [s] serial i/o shift register 30 (sio30) 287 serial i/o shift register 31 (sio31) 287 serial operation mode register 30 (csim30) 288, 289, 290 serial operation mode register 31 (csim31) 288, 289, 290 16-bit timer mode control register (tmc0) 162 16-bit timer output control register (toc0) 165 16-bit timer register (tm0) 160 slave address register (sva0) 296, 303
435 appendix d register index [t] timer clock selection register 50 (tcl50) 192 timer clock selection register 51 (tcl51) 192 transmit shift register (txs0) 264 [w] watch timer mode control register (wtm) 211 watchdog timer clock select register (wdcs) 218 watchdog timer mode register (wdtm) 219
436 appendix d register index d.2 register index (in alphabetical order with respect to register symbol) [a] adcr0 : a/d conversion result register 0 230, 245 adm0 : a/d converter mode register 232, 249 ads0 : analog input channel specification register 234, 251 asim0 : asynchronous serial interface mode register 265, 269 asis0 : asynchronous serial interface status register 267, 271 [b] brgc0 : baud rate generator control register 267, 272 [c] crc0 : capture/compare control register 164 cr00 : capture/compare register 00 161 cr01 : capture/compare register 01 162 cks : clock output selection register 224 cr50 : 8-bit compare register 50 191 cr51 : 8-bit compare register 51 191 csim30 : serial operation mode register 30 288, 289, 290 csim31 : serial operation mode register 31 288, 289, 290 [e] egn : external interrupt falling edge enable register 235, 251, 357 egp : external interrupt rising edge enable register 235, 251, 357 [i] if0h : interrupt request flag register 0h 354 if0l : interrupt request flag register 0l 354 if1l : interrupt request flag register 1l 354 iic0 : iic shift register 296, 303 iicc0 : iic control register 297 iiccl0 : iic clock select register 304 iics0 : iic status register 301 ims : memory size switching register 395 [m] mem : memory expansion mode register 372 mk0h : interrupt mask flag register 0h 355 mk0l : interrupt mask flag register 0l 355 mk1l : interrupt mask flag register 1l 355 mm : memory expansion wait setting register 373 [o] osts : oscillation stabilization time select register 382
437 appendix d register index [p] p0 : port 0 124 p1 : port 1 125 p2 : port 2 126 p3 : port 3 127, 129 p4 : port 4 132 p5 : port 5 133 p6 : port 6 134 p7 : port 7 135 pcc : processor clock control register 143 pm0 : port mode register 0 136 pm2 : port mode register 2 136 pm3 : port mode register 3 136 pm4 : port mode register 4 136 pm5 : port mode register 5 136 pm6 : port mode register 6 136 pm7 : port mode register 7 136, 167, 195, 226 pr0h : priority specify flag register 0h 356 pr0l : priority specify flag register 0l 356 pr1l : priority specify flag register 1l 356 prm0 : prescaler mode register 166 psw : program status word 100, 358 pu0 : pull-up resistor option register 0 138 pu2 : pull-up resistor option register 2 138 pu3 : pull-up resistor option register 3 138 pu4 : pull-up resistor option register 4 138 pu5 : pull-up resistor option register 5 138 pu6 : pull-up resistor option register 6 138 pu7 : pull-up resistor option register 7 138 [r] rxb0 : receive buffer register 264 rxs0 : receive shift register 264 [s] sio30 : serial i/o shift register 30 287 sio31 : serial i/o shift register 31 287 sva0 : slave address register 296, 303
438 appendix d register index [t] tcl50 : timer clock selection register 50 192 tcl51 : timer clock selection register 51 192 tm0 : 16-bit timer register 160 tm50 : 8-bit counter 50 191 tm51 : 8-bit counter 51 191 tmc0 : 16-bit timer mode control register 162 tmc50 : 8-bit timer mode control register 50 193 tmc51 : 8-bit timer mode control register 51 193 toc0 : 16-bit timer output control register 165 txs0 : transmit shift register 264 [w] wdcs : watchdog timer clock select register 218 wdtm : watchdog timer mode register 219 wtm : watch timer mode control register 211
439 appendix e revision history the following shows the revision history up to present. application portions signifies the chapter of each edition. (1/3) edition no. main revised contents from old edition revised sections 2nd edition recommended connection of unused ic, vpp pins changed connect directly to v ss0 ? connect directly to v ss0 or v ss1 cautions about set value added to capture/compare register 00 (cr00) and capture/compare register 01 (cr01) added cautions about contending operations added descriptions when tm50, tm51, and cr50, cr51 are used when tm50 and tm51 are connected in cascade configuration added. diagram of square-wave output operations timing added interrupt request generating time interval of watch timer revised 0.5 second ? 0.5 or 0.25 second block diagram of watchdog timer revised block diagram of clock output/buzzer output control circuit revised cautions at selecting conversion time added to a/d converter mode register (adm0) format cautions about first a/d conversion value just after a/d conversion start added a/d conversion by hardware start (when falling edge is specified) and a/d conversion by software start revised baud rate generator control register (brgc0) format revised ? n value changed ? cautions when using infrared data transfer mode added descriptions about receive completion interrupt (intsr0) generation timing when receive error is generated added available bit rate at infrared data transfer mode changed iic clock select register (iiccl0) format revised ? setting details of cl00 bit revised ? cautions at transfer rate change added procedure of communication reservation revised chapter 3 pin func- tion ( m pd780024, 780034 subseries), chapter 4 pin func- tion ( m pd780024y, 780034y subseries) chapter 8 16-bit timer/event counter chapter 9 8-bit timer/ event counter chapter 10 watch timer chapter 11 watch- dog timer chapter 12 clock output/buzzer output control circuit chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries), chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) chapter 16 serial interface (uart0) chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only)
440 appendix e revision history (2/3) edition no. main revised contents from old edition revised sections 2nd edition the following two items removed from external interrupt ? detect t100/p70/to0 pin input edge ? detect t101/p71 pin input edge data hold voltage at stop mode changed 1.8 v ? 1.6 v a/d converter in halt mode operating statuses revised operation enable ? operation halt clock output/buzzer output control circuit in stop mode operating status added ? df780024 added to device file ? the product name of flash programmer changed flashpro ? flashpro ii (cavity no. fl-pr2) ? the product name of flash memory writing adapter changed pa-flash64cw ? fa-64cw, pa-flash64gc ? fa-64gc, pa-flash64gk ? fa-64gk ? the product name of in-circuit emulator changed ie-780000-sl ? ie-78001-r-a ? cpu core board(ie-78k0-sl-em) removed ? the product name of conversion socket changed ev-9200gc-64 ? tgc-064sap ? former edition, development environment when using ie-78000-r-a removed 3rd edition caution about a/d conversion result register (adcr0) read operation added. caution about setting of port mode register and output latch is added. description of lrel0 flag of iic control register (iicc0) revised. communication reservation check method changed. description revised: in-circuit emulator ie-78k0-ns is supported. description revised: fuzzy inference development support system is deleted. chapter 19 inter- rupt functions chapter 21 standby functions appendix b devel- opment tools chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries), chapter 14 10-bit a/d converter ( m pd780034, 780034y subseries) chapter 16 serial interface (uart0), chapter 17 serial interface (sio3), chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only) chapter 18 serial interface (iic0) ( m pd780024, 780024y subseries only) appendix b devel- opment tools appendix c embed- ded software
441 appendix e revision history (3/3) edition no. main revised contents from old edition revised sections 4th edition addition of caution regarding setting values for memory size switching register to 5.1 memory spaces change and addition of caution to 8.3 16-bit timer/event counter configu- ration (2) capture/compare register00(cr00), (3) capture/compare register01(cr01) change in figure 8-2 16-bit timer mode control register (tmc0) format addition of caution to figure 8-3 capture/compare control register 0 (crc0) format addition of note to figure 8-4 16-bit timer output control register (toc0) format change and addition of caution to figure 8-5 prescaler mode register 0 (prm0) format addition of caution to figure 8-10 control register settings for ppg output operation addition of caution to figure 8-10 control register settings for ppg output operation revision of following timing charts figure 8-13 timing of pulse width measurement operation by free- running counter and one capture register (with both edges specified) figure 8-16 timing of pulse width measurement operation with free- running counter (with both edges specified) figure 8-18 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) figure 8-20 timing of pulse width measurement operation by means of restart (with rising edge specified) addition of caution to 8.5.4 external event counter operation 8.5.6 one-shot pulse output operation first sentence about prohibition of one-shot pulse output with external trigger completely changed 8.6 16-bit timer/event counter operating precautions revision in (7) operation of ovf0 flag addition of the following items (9) timer operation (10) capture operation (11) compare operation (12) edge detection revision of caution of 13.2 a/d converter configuration, (2) a/d conversion result register (adcr0) revision in 13.5 a/d converter cautions, (10) a/d conversion result register (adcr0) read operation revision of caution of 14.2 a/d converter configuration, (2) a/d conversion result register (adcr0) revision in 14.5 a/d converter cautions, (10) a/d conversion result register (adcr0) read operation addition of note to figure 17-2 serial interface (sio30) configuration revision of 18.3 registers to control serial interface, (1) iic control register (iicc0) revision of explanations of stt0 and spt0 flags in figure 18-3 iic control register (iicc0) format chapter 5 cpu architecture chapter 8 16-bit timer/event counter chapter 13 8-bit a/d converter ( m pd780024, 780024y subseries) chapter 14 10-bit a/ d converter ( m pd780034, 780034y subseries) chapter 17 serial interface (sio3) chapter 18 serial interface (iic0) ( m pd780024y, 780034y subseries only)
442 [memo]
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